DS26514G Maxim Integrated, DS26514G Datasheet - Page 26

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

19-5856; Rev 4; 5/11
SCANMODE
REFCLKIO
DIGIOEN
RESETB
ATVDD
ARVDD
ARVSS
ACVDD
ATVSS
JTCLK
NAME
MCLK
JTRST
JTMS
JTDO
JTDI
M1, M16,
M2, M15,
G1, G16,
G2, G15,
D1, D16,
D2, D15,
B1, B16,
K1, K16,
B2, B15,
K2, K15,
E1, E16,
E2, E15,
R1, R16
R2, R15
N1, N16
N2, N15
H13
PIN
J12
B7
A7
D8
K4
F5
H4
H7
L5
J4
Impedance
Output,
Output
Pullup
Pullup
Pullup
Pullup
TYPE
Input/
Input,
Input,
Input,
Input,
Input
Input
Input
Input
High
—
—
—
—
—
Master Clock. This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLKn must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See
Reset Bar. Active-low reset. This input forces the complete DS26514 reset. This
includes reset of the registers, framers, and LIUs.
Reference Clock Input/Output
Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the users to synchronize the system
backplane with the reference clock. The other options for the backplane clock
reference are LIU-received clocks or MCLK.
Output: This signal can also be used to output a 1.544MHz or 2.048MHz
reference clock. This allows for multiple DS26514s to share the same reference
for generation of the backplane clock. Hence, in a system consisting of multiple
DS26514s, one can be a master and others a slave using the same reference
clock.
Digital Enable. When this pin and JTRST are pulled low, all digital I/O pins are
placed in a high-impedance state. If this pin is high the digital I/O pins operate
normally. This pin must be connected to V
JTAG Reset. JTRST is used to asynchronously reset the test access port
controller. After power-up, JTRST must be toggled from low to high. This action
sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores
normal device operation. JTRST is pulled high internally via a 10kΩ resistor
operation. If boundary scan is not used, this pin should be held low.
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used
to place the test access port into the various defined IEEE 1149.1 states. This pin
has a 10kΩ pullup resistor.
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge.
JTAG Data In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Data Out. Test instructions and data are clocked out of this pin on the
falling edge of JTCLK. If not used, this pin should be left unconnected.
Scan Mode. When low, normal operational clocks are used to clock the flip flops.
User should tie low.
3.3V ±5% Analog Transmit Power Supply. These V
transmit LIU sections of the DS26514.
Analog Transmit V
3.3V ±5% Analog Receive Power Supply. These V
receive LIU sections of the DS26514.
Analog Receive V
1.8V ±5% Analog Clock Conversion V
conversion unit (CLAD) of the DS26514.
POWER SUPPLIES
TEST
Table
SS
SS
. These pins are used for analog V
10-15.
. These pins are used for transmit analog V
FUNCTION
DS26514 4-Port T1/E1/J1 Transceiver
DD
DD
. This V
for normal operation.
DD
DD
input is used for the clock
DD
inputs are used for the
SS
inputs are used for the
for the receivers.
SS
.
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