DS26514G Maxim Integrated, DS26514G Datasheet - Page 263

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The FIFO data and status are updated when the Receive FIFO Data (RH256FDR2.RFD[7:0]) is read.
Reading this register will reflect the status of the next read of RH256FDR2.
Bits 3 to 1: Receive Packet Status (RPS[2:0]) – These three bits indicate the status of the received packet and
packet data.
Bit 0: Receive FIFO Data Valid (RFDV) – When 0, the Receive FIFO data (RFD[7:0]) is invalid (the Receive FIFO
is empty). When 1, the Receive FIFO data (RFD[7:0]) is valid.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: Reading this register when RH256FDR1.RFDV=0 may result in a loss of data.
Bits 7 to 0: Receive FIFO Data (RFD[7:0]) – These eight bits are the packet data stored in the Receive FIFO.
RFD[7] is the MSB, and RFD[0] is the LSB. If bit reordering is disabled, RFD[0] is the first bit received, and RFD[7]
is the last bit received. If bit reordering is enabled, RFD[7] is the first bit received, and RFD[0] is the last bit
received.
19-5856; Rev 4; 5/11
000 = packet middle
001 = packet start.
010 = reserved
011 = reserved
100 = packet end: good packet
101 = packet end: FCS errored packet.
110 = packet end: invalid packet (a non-integer number of bytes).
111 = packet end: aborted packet.
RFD7
--
X
7
0
7
RFD6
--
X
6
0
6
RH256FDR1
Receive HDLC-256 FIFO Data Register 1
151Ch + (20h x (n-1)) : where n = 1 to 4
RH256FDR2
Receive HDLC-256 FIFO Data Register 2
151Dh + (20h x (n-1)) : where n = 1 to 4
RFD5
--
X
5
0
5
RFD4
--
X
4
0
4
RPS2
RFD3
X
X
3
3
DS26514 4-Port T1/E1/J1 Transceiver
RPS1
RFD2
X
X
2
2
RPS0
RFD1
X
X
1
1
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RFDV
RFD0
X
0
0
0