DS26514G Maxim Integrated, DS26514G Datasheet - Page 131

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]). These bits select which reference clock
source will be used for BPCLK1 generation. The BPCLK1 can be generated from LIU’s 1 to 4 recovered clocks, an
external reference, or derivatives of MCLK input. This is shown in
information.
Bit 3: Backplane Frequency Select (BFREQSEL). In conjunction with BPRFSEL[3:0], this bit identifies the
reference clock frequency used by the DS26514 backplane clock generation circuit. Note that the setting of this bit
should match the T1E1 selection for the LIU whose recovered clock is being used to generate the backplane clock.
See
Bit 2: Frequency Selection (FREQSEL). In conjunction with the MPS[1:0] bits, this bit selects the external MCLK
frequency of the signal input at the MCLK pin of the DS26514.
Bits 1 and 0: Master Period Select 1 and 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select
the external MCLK frequency of the signal input at the MCLK pin of the DS26514. This is shown in
Table 10-15. Master Clock Input Selection
19-5856; Rev 4; 5/11
FREQSEL
Figure 9-9
0
0
0
0
1
1
1
1
0 = Backplane reference clock is 2.048MHz.
1 = Backplane reference clock is 1.544MHz.
0 = The external master clock is 2.048MHz or multiple thereof.
1 = The external master clock is 1.544MHz or multiple thereof.
BPREFSEL3
MPS1
for additional information.
0
0
1
1
0
0
1
1
7
0
MPS0
0
1
0
1
0
1
0
1
GTCCR1
Global Transceiver Clock Control Register 1
00F3h
BPREFSEL2
6
0
(MHz ±50ppm)
16.384
12.352
MCLK
2.048
4.096
8.192
1.544
3.088
6.176
BPREFSEL1
5
0
BPREFSEL0
4
0
BFREQSEL
Table
3
0
DS26514 4-Port T1/E1/J1 Transceiver
10-16. See
FREQSEL
2
0
Figure 9-9
MPS1
1
0
Table
for additional
131 of 305
10-15.
MPS0
0
0