DS26514G Maxim Integrated, DS26514G Datasheet - Page 302

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

14.3 JTAG ID Codes
Table 14-2. ID Code Structure
14.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An
optional test register, the Identification Register, has been included with the DS26514 design. The Identification
Register is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
14.4.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells,
and is n bits in length.
14.4.2 Bypass Register
This register is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, providing a short path between JTDI and JTDO.
14.4.3 Identification Register
The Identification Register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
19-5856; Rev 4; 5/11
DS26519
DS26518
DS26514
DEVICE
Consult factory
Consult factory
Consult factory
REVISION
ID[31:28]
0000000010001011
0000000010001010
0000000010001100
DEVICE CODE
ID[27:12]
MANUFACTURER’S CODE
00010100001
00010100001
00010100001
ID[11:1]
DS26514 4-Port T1/E1/J1 Transceiver
REQUIRED
ID[0]
1
1
1
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