DS26514G Maxim Integrated, DS26514G Datasheet - Page 225

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can cause interrupts.
Bit 7: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is
deleted.
Bit 6: Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a
frame is repeated.
Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP). Set when the transmit elastic store has either
repeated or deleted a frame.
Bit 4: Transmit SLC-96 Multiframe Event (TSLC96) (T1 Mode Only). When enabled by T1.TCR2.6, this bit will
set once per SLC-96 multiframe (72 frames) to alert the host that new data may be written to the T1TSLC1–3
registers. See Section
Bit 3: Transmit Align Frame Event (TAF) (E1 Mode Only). Set every 250µs to alert the host that the
E1TNAF
Bit 2: Transmit Multiframe Event (TMF). In T1 mode, this bit is set every 1.5ms on D4 MF boundaries or every
3ms on ESF MF boundaries. In E1 operation, this but is set every 2ms (regardless if CRC-4 is enabled) on transmit
multiframe boundaries. Used to alert the host that signaling data needs to be updated.
Bit 1: Loss of Transmit Clock Condition Clear (LOTCC). Set when the LOTC condition has cleared (a clock has
been sensed at the TCLKn pin).
Bit 0: Loss of Transmit Clock Condition (LOTC). Set when the TCLKn pin has not transitioned for approximately
3 clock periods. Will force the LOTC pin high if enabled. This bit can be cleared by the host even if the condition is
still present. The LOTC pin will remain high while the condition exists, even if the host has cleared the status bit. If
enabled by TIM1.0, the INTB pin will transition low when this bit is set, and transition high when this bit is cleared (if
no other unmasked interrupt conditions exist).
19-5856; Rev 4; 5/11
registers need to be updated.
TESF
TESF
7
0
9.9.4.3
TLS1
Transmit Latched Status Register 1
190h + (200h x (n - 1)) : where n = 1 to 4
TESEM
TESEM
6
0
for more information.
TSLIP
TSLIP
5
0
TSLC96
—
4
0
—
TAF
3
0
DS26514 4-Port T1/E1/J1 Transceiver
TMF
TMF
2
0
LOTCC
LOTCC
1
0
E1TAF
225 of 305
LOTC
LOTC
0
0
and