DS26514G Maxim Integrated, DS26514G Datasheet - Page 252

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All latched bits in this register can create interrupts.
Bit 6: BERT Bit Error Detected (BED) Event (BBED). A latched bit, which is set when a bit error is detected. The
receive BERT must be in synchronization for it to detect bit errors.
Bit 5: Real-time BERT All Zeros or Ones (RBA01). Or’d real time status of all zero detection and all ones
detection.
Bit 4: Real-time Sync (RSYNC). Real time sync status. A zero indicates not synchronized and a one indicates
synchronization state.
Bit 3: BERT Receive All-Ones Condition (BRA1). A latched bit, which is set when 32 consecutive ones are
received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). A latched bit, which is set when 32 consecutive zeros are
received.
Bit 1: BERT Receive Loss Of Synchronization Condition (BRLOS). A latched bit which is set whenever the
receive BERT begins searching for a pattern.
Bit 0: BERT in Synchronization Condition (BSYNC). A latched bit that is set when the incoming pattern matches
for 32 consecutive bit positions.
19-5856; Rev 4; 5/11
—
7
0
BSR
BERT Status Register
110Eh + (10h x (n - 1)) : where n = 1 to 4
BBED
6
0
RBRA01
5
0
RSYNC
4
0
BRA1
3
0
DS26514 4-Port T1/E1/J1 Transceiver
BRA0
2
0
BRLOS
1
0
252 of 305
BSYNC
0
0