DS26514G Maxim Integrated, DS26514G Datasheet - Page 23

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

19-5856; Rev 4; 5/11
RSYSCLK2/
RSYSCLK3/
RSYSCLK4/
RSYSCLK1
RMSYNC1/
RMSYNC2/
RMSYNC3/
RMSYNC4/
RFSYNC1
RFSYNC2
RFSYNC3
RFSYNC4
RLF/LTC2
RLF/LTC3
RLF/LTC4
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSER1
RSER2
RSER3
RSER4
RCLK1
RCLK2
RCLK3
RCLK4
RSIG1
RSIG2
RSIG3
RSIG4
NAME
PIN
L12
G4
M4
M3
M5
E5
D6
N4
N6
F4
E3
N3
A4
B6
N5
T6
C4
C6
P4
P6
D4
E6
R5
L4
Input with
pulldown/
internal
Output
Output
Output
Output
Output
Output
TYPE
Input/
Input
Received Serial Data 1 to 4. Received NRZ serial data. Updated on rising edges
of RCLKn when the receive-side elastic store is disabled. Updated on the rising
edges of RSYSCLKn when the receive-side elastic store is enabled.
When IBO mode is used, the RSERn pins can output data for multiple framers.
The RSERn data is synchronous to RSYSCLKn. See Section
9-6
Receive Clock 1 to 4. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to
clock data through the receive-side framer. This clock is recovered from the
signal at RTIPn and RRINGn. RSERn data is output on the rising edge of RCLKn.
RCLKn is used to output RSERn when the elastic store is not enabled or IBO is
not used. When the elastic store is enabled or IBO is used, the RSERn is clocked
by RSYSCLKn.
Receive System Clock 1. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic
store function is enabled. Should be tied low in applications that do not use the
receive-side elastic store. Multiple of 2.048MHz is expected when the IBO mode
is used. Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the master
RSYSCLK for all framers.
Receive System Clock 2 to 4. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic
store function is enabled. Should be tied low in applications that do not use the
receive-side elastic store. Multiple of 2.048MHz is expected when the IBO Mode
is used.
Receive Loss of Frame/Loss of Transmit Clock. This pin can also be
programmed to either toggle high when the synchronizer is searching for the
frame and multiframe or to toggle high if the TCLKn pin has not been toggled for
approximately three clock periods.
RLF/LTC[4:2] are available when GTCR1.528MD = 1.
Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the master
RSYSCLK for all framers.
Receive Synchronization 1 to 4. If the receive-side elastic store is enabled, this
signal is used to input a frame or multiframe boundary pulse. If set to output
frame boundaries, RSYNCn can be programmed to output double-wide pulses on
signaling frames in T1 mode. In E1 mode, RSYNCn out can be used to indicate
CAS and CRC-4 multiframe. The DS26514 can accept an H.100-compatible
synchronization signal. The default direction of this pin at power-up is input, as
determined by the RSIO control bit in the RIOCR.2 register.
Receive Multiframe/Frame Synchronization 1 to 4. A dual function pin to
indicate frame or multiframe synchronization. RFSYNCn is an extracted 8kHz
pulse, one RCLKn wide that identifies frame boundaries. RMSYNCn is an
extracted pulse, one RCLKn wide (elastic store disabled) or one RSYSCLKn wide
(elastic store enabled), that identifies multiframe boundaries. When the receive
elastic store is enabled, the RMSYNCn signal indicates the multiframe sync on
the system (backplane) side of the elastic store. In E1 mode, this pin can indicate
either the CRC-4 or CAS multiframe as determined by the RSMS2 control bit in
the Receive I/O Configuration register (RIOCR.1).
Receive Signaling 1 to 4. Outputs signaling bits in a PCM format. Updated on
rising edges of RCLKn when the receive-side elastic store is disabled. Updated
on the rising edges of RSYSCLKn when the receive-side elastic store is enabled.
See
Table 9-7
RECEIVE FRAMER
.
FUNCTION
DS26514 4-Port T1/E1/J1 Transceiver
9.8.2
and
23 of 305
Table