DS26514G Maxim Integrated, DS26514G Datasheet - Page 196

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Bits 7 to 0: Channel Blocking Control Bits for Receive Channels 1 to 32 (CH[1:32])
*Note that RCBR4 has two functions:
Register Name:
Register Description:
Register Address:
Bit #
Name
Setting any of the CH[1:24] bits in the RSI1 through RSI4 registers will cause signaling data to be reinserted for the
associated channel. RSI4 is used for 2.048MHz backplane operation.
19-5856; Rev 4; 5/11
0 = Force the RCHBLKn pin to remain low during this channel time.
1 = Force the RCHBLKn pin high during this channel time.
When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking
signal for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the
RCHBLKn signal will pulse high during the F-bit time. In this mode RCBR4.1 to RCBR4.7 should be set to
0.
(MSB)
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
CH8
CH8
7
7
RCBR4.0 = 0, do not pulse RCHBLKn during the F-bit.
RCBR4.0 = 1, pulse RCHBLKn during the F-bit.
CH15
CH23
CH31
CH15
CH23
CH31
CH7
CH7
6
6
RCBR1, RCBR2, RCBR3, RCBR4
Receive Channel Blocking Registers 1 to 4
0C4h, 0C5h, 0C6h, 0C7h + (200h x (n - 1)) : where n = 1 to 4
RSI1, RSI2, RSI3, RSI4
Receive-Signaling Reinsertion Enable Registers 1 to 4
0C8h, 0C9h, 0CAh, 0CBh + (200h x (n - 1)) : where n = 1 to 4
CH14
CH22
CH30
CH14
CH22
CH30
CH6
CH6
5
5
CH13
CH21
CH29
CH13
CH21
CH29
CH5
CH5
4
4
CH12
CH20
CH28
CH12
CH20
CH28
CH4
CH4
3
3
CH11
CH19
CH27
CH11
CH19
CH27
CH3
CH3
2
2
CH10
CH18
CH26
CH10
CH18
CH26
CH2
CH2
1
1
DS26514 4-Port T1/E1/J1 Transceiver
(F-bit)
(LSB)
CH17
CH25
CH1
CH9
(LSB)
CH17
CH25
CH1
CH9
0
0
RCBR1
RCBR2
RCBR3
RCBR4 (E1
Mode Only)*
RSI1
RSI2
RSI3
RSI4 (E1
Mode Only)
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