DS26514G Maxim Integrated, DS26514G Datasheet - Page 234

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Bits 7 to 0: Transmit Channels 1 to 32 Gapped Clock Channel Select Bits (CH[1:32])
* Note that TGCCS4 has two functions:
Register Name:
Register Description:
Register Address:
Bit #
Name
Bits 7 to 0: Per-Channel Loopback Enable for Channels 1 to 32 (CH[1:32])
19-5856; Rev 4; 5/11
0 = no clock is present on TCHCLK during this channel time
1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLKn if the
elastic store is disabled, and synchronous with TSYSCLKn if the elastic store is enabled.
When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on
TCHCLK for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is
generated on TCHCLK during the F-bit time:
In this mode TGCCS4.1 to TGCCS4.7 should be set to 0.
0 = Loopback disabled.
1 = Enable loopback. Source data from the corresponding receive channel.
(MSB)
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
CH8
CH8
7
7
TGCCS4.0 = 0, do not generate a clock during the F-bit.
TGCCS4.0 = 1, generate a clock during the F-bit.
CH15
CH23
CH31
CH15
CH23
CH31
CH7
CH7
TGCCS1, TGCCS2, TGCCS3, TGCCS4
Transmit Gapped Clock Channel Select Registers 1 to 4
1CCh, 1CDh, 1CEh, 1CFh + (200h x (n - 1)) : where n = 1 to 4
PCL1, PCL2, PCL3, PCL4
Per-Channel Loopback Enable Registers 1 to 4
1D0h, 1D1h, 1D2h, 1D3h + (200h x (n - 1)) : where n = 1 to 4
6
6
CH14
CH22
CH30
CH14
CH22
CH30
CH6
CH6
5
5
CH13
CH21
CH29
CH13
CH21
CH29
CH5
CH5
4
4
CH12
CH20
CH28
CH12
CH20
CH28
CH4
CH4
3
3
CH11
CH19
CH27
CH11
CH19
CH27
CH3
CH3
2
2
DS26514 4-Port T1/E1/J1 Transceiver
CH10
CH18
CH26
CH2
CH10
CH18
CH26
CH2
1
1
(F-bit)
(LSB)
CH17
CH25
CH1
CH9
CH17
CH25
(LSB)
CH1
CH9
0
0
TGCCS1
TGCCS2
TGCCS3
TGCCS4 (E1
Mode Only)*
PCL1
PCL2
PCL3
PCL4 (E1
Mode Only)
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