DS26514G Maxim Integrated, DS26514G Datasheet - Page 220

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: u-Law or A-Law Digital Milliwatt Code Select (uALAW)
Bits 6 and 5: Transmit Bit Inversion (BINV[1:0])
Bit 4: Transmit Jammed Bit 8 Suppression Enable (TJBEN)
Bits 3: Transmit RAI Mode (TRAIM) (T1 Mode Only). Determines the pattern sent when TRAI (TCR1.0) is
activated in ESF frame mode only.
Bits 2 : Transmit AIS Mode (TAISM) (T1 Mode Only). Determines the pattern sent when TAIS (TCR1.1) is
activated.
Bits 1 and 0 : Transmit Code Length Definition Bits (TC[1:0]) (T1 Mode Only)
19-5856; Rev 4; 5/11
TC1
0
0
1
1
0 = u-law code is inserted based on TDMWEx registers.
1 = A-law code is inserted based on TDMWEx registers.
00 = No inversion.
01 = Invert framing.
10 = Invert signaling.
11 = Invert payload.
0 = No stuffing enabled.
1 = Jammed Bit 8 Suppression enabled. This forces bit 8 to a one as determined by TJBE1–4 registers
and bit 7 to a one in T1 signaling frames.
0 = Transmit normal RAI when TCR1.RAI = 1
1 = If T1 ESF mode, transmit RAI-CI (T1.403) when TCR1.RAI = 1
0 = Transmit normal AIS (unframed all ones) upon activation with TCR1.1.
1 = Transmit AIS-CI (T1.403) upon activation with TCR1.1.
TC0
0
1
0
1
uALAW
uALAW
7
0
16 bits : 8 bits : 4 bits : 2 bits : 1 bit
TCR4
Transmit Control Register 4
186h + (200h x (n - 1)) : where n = 1 to 4
BINV1
BINV1
6
0
Length Selected
6 bits : 3 bits
5 bits
7 bits
BINV0
BINV0
5
0
TJBEN
TJBEN
4
0
TRAIM
—
3
0
DS26514 4-Port T1/E1/J1 Transceiver
TAISM
—
2
0
TC1
—
1
0
220 of 305
TC0
—
0
0