DS26514G Maxim Integrated, DS26514G Datasheet - Page 180

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Note: Status bits in this register are latched.
When a channel’s signaling data changes state, the respective bit in registers RSS1–4 will be set and latched. The
RSCOS bit (RLS4.3) will be set if the channel was also enabled by setting the appropriate bit in RSCSE1–4. The
INTB signal will go low if enabled by the interrupt mask bit RIM4.3. The bit will remain set until read.
*
represents reserved bits and the distant multiframe alarm.
19-5856; Rev 4; 5/11
Note that in E1 CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of
(MSB)
CH16
CH24
CH32
CH8
7
CH15
CH23
CH31
CH7
RSS1, RSS2, RSS3, RSS4
Receive-Signaling Status Registers 1 to 4
098h, 099h, 09Ah, 09Bh + (200h x (n - 1)) : where n = 1 to 4
6
CH14
CH22
CH30
CH6
5
CH13
CH21
CH29
CH5
4
CH12
CH20
CH28
CH4
3
CH11
CH19
CH27
CH3
2
DS26514 4-Port T1/E1/J1 Transceiver
CH10
CH18
CH26
CH2
1
CH17*
CH25
(LSB)
CH1*
CH9
0
RSS1
RSS2
RSS3
RSS4 (E1
Mode Only)
180 of 305
RSS3