PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 98

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Table 6-2. VI unit interface pins
6.1.2
The VI logic can be set to operate in diagnostic mode,
which connects the inputs of VI to the outputs of the EVO
6-2
VI_CLK
VI_DVALID
VI_DATA[7:0]
VI_DATA[9:8]
Diagnostic Mode
I/O-5 • If configured as input (power up
IN-5
IN-5
IN-5
• If configured as output: programma-
• See
VI_DVALID indicates that valid data is
present on the VI_DATA lines. If
HIGH, VI_DATA will be accepted on
the next VI_CLK positive edge. If
LOW, no VI_DATA will be sampled.
PNX1300 supports an additional mode
where VI_DATA[9:8] in message pass-
ing mode are not affected by the
VI_DVALID signal,
CCIR656 style YUV 4:2:2 data from a
digital camera, or general purpose
high speed data input pins. Sampled
on positive transitions of VI_CLK if
VI_DVALID HIGH.
Extension high speed data input bits to
allow use of 10-bit video A/D convert-
ers in raw10 modes. VI_DATA[8]
serves as START and VI_DATA[9] as
END message input in message pass-
ing mode. Sampled on positive transi-
tions of VI_CLK if VI_DVALID HIGH.
PNX1300 supports an additional mode
where VI_DATA[9:8] in message pass-
ing mode are not affected by the
VI_DVALID signal,
PRELIMINARY SPECIFICATION
default): a positive transition on this
incoming video clock pin samples
all other VI_DATA input signals
below if VI_DVALID is HIGH. If
VI_DVALID is LOW, VI_DATA is
ignored. Clock and data rates of up
to 81 MHz are supported. PNX1300
supports an additional mode where
VI_DATA[9:8] in message passing
mode are not affected by the
VI_DVALID signal,
ble output clock to drive an external
video A/D converter. Can be pro-
grammed to emit integral dividers of
DSPCPU_CLK.
ming details.
Section 6.2
Section
Section
for clock program-
Section
6.6.1.
6.6.1.
6.6.1.
unit. This mode provides boot diagnostics with the ability
to verify major operational aspects of the chip before
handing control to an operating system.
Diagnostic mode is entered by writing a control word with
a ‘1’ in the DIAGMODE bit position to the VI_CTL register
(see
vide a clock before starting DIAGMODE. After a VI soft-
ware reset, the DIAGMODE bit has to be set back to ‘1’.
In diagnostic mode, the VI signals are exactly as shown
in
chip EVO unit. Note that the inputs are truly taken from
the PNX1300 EVO external pins, i.e. if an external (board
level) source is driving EVO pins, diagnostic mode is not
capable of testing the EVO unit.
Note that the diagnostic mode only controls an input mul-
tiplexer. VI can be programmed and operated in all usual
modes. The raw modes are particularly attractive for di-
agnostics purposes, since they allow VI to operate al-
most as an on-chip logic analyzer.
6.1.3
The VI unit enters power down state whenever PNX1300
is put in global power down mode, except if the SLEEP-
LESS bit in VI_CTL is set. In the latter case, the block
continues DMA operation and will wake up the DSPCPU
whenever an interrupt is generated.
The EVO block can be separately powered down by set-
ting a bit in the BLOCK_POWER_DOWN register. Refer
to
It is recommended that the EVO unit be stopped (by ne-
gating VI_CTL.CAPTURE_ENABLE) before block-level
power down is started, or that SLEEPLESS mode be
used when global power down is activated.
6.1.4
Video In is reset by a PNX1300 hardware reset (pin
TRI_RESET#) or by a VI software reset. The latter is ac-
complished by writing a control word of 0x00080000 to
the VI_CTL register. After a software reset, allow for 5
video clock cycles delay before enabling VI capture.
Upon hardware or software reset, the VI_CTL,
VI_STATUS, and VI_CLOCK registers are set to all ’0’s.
The state of the other registers after RESET is unde-
Chapter 21, “Power Management.”
Figure
Figure
6-2, except that the inputs come from the on-
Power Down and Sleepless
Hardware and Software Reset
6-11). The EVO unit has to be setup to pro-
Philips Semiconductors