PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 428

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
32-bit load with displacement
SYNTAX
FUNCTION
DESCRIPTION
in rdest. The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a multiple of 4. If
the memory address computed by rsrc1 + d is not a multiple of 4, the result of
will be raised. This load operation is performed as little-endian or big-endian depending on the current setting of the
bytesex bit in the PCSW.
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
r10 = 0xcfc,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
r30 = 0, r20 = 0xd0c,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r40 = 1, r20 = 0xd0c,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r50 = 0xd01
The
The
The
[ IF rguard ] ld32d(d) rsrc1 → rdest
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
rdest<7:0> ← mem[rsrc1 + d + (3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + d + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + d + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + d + (0 ⊕ bs)]
ld32d
ld32d
ld32d
bs ← 3
bs ← 0
Initial Values
ld32d
operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
operation loads the 32-bit memory value from the address computed by rsrc1 + d and stores the result
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
has no side effects whatever.
ld32d(4) r10 → r60
IF r30 ld32d(-8) r20 → r70
IF r40 ld32d(-8) r20 → r80
ld32d(-8) r50 → r90
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
r60 ← 0x84332211
no change, since guard is false
r80 ← 0x48665544
r90 undefined, since 0xd01 +(–8) is not a
multiple of 4
ld32d
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ld32 ld32r ld32x st32
is undefined but no exception
st32d h_st32d
ATTRIBUTES
SEE ALSO
Result
–256..252 by 4
ld32d
ld32d
dmem
7 bits
4, 5
7
1
3
A-130
.