PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 104

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
cluding CUR_Y have been written to local SDRAM upon
THRESHOLD REACHED. The implementation guaran-
tees a fixed maximum time of 2 µs between raising the
interrupt and completion of all writes to SDRAM. The
Figure 6-11. YUV capture view of VI MMIO registers.
If VI internal buffers overflow due to insufficient internal
data-highway bandwidth allocation, the HIGHWAY
BANDWIDTH ERROR condition is raised in the
VI_STATUS register. If enabled, this causes assertion of
a VI interrupt request. Capture continues at the correct
memory address as soon as the internal buffers can be
written to memory, but one or more pixels may have
been lost, and the corresponding memory locations are
not written. The HBE condition can be cleared by writing
a ‘1’ to the HIGHWAY BANDWIDTH ERROR ACK bit in
VI_CTL. Refer to
HBE”
Any interrupt event of VI (CAPTURE COMPLETE,
THRESHOLD REACHED, HIGHWAY BANDWIDTH ER-
ROR) leads to the assertion of a single VI interrupt
6-8
MMIO_base
0x10 140C
0x10 141C
0x10 1400
0x10 1404
0x10 1408
0x10 1410
0x10 1414
0x10 1418
0x10 1420
0x10 1424
offset:
for more information.
VI_STATUS (r)
VI_CTL (r/w)
VI_CLOCK (r/w)
VI_CAP_START (r/w)
VI_CAP_SIZE (r/w)
VI_Y_BASE_ADR (r/w)
VI_U_BASE_ADR (r/w)
VI_V_BASE_ADR (r/w)
VI_UV_DELTA (r/w)
VI_Y_DELTA (r/w)
Section 6.7, “Highway Latency and
PRELIMINARY SPECIFICATION
Highway bandwidth error ACK
31
software RESET
DIAGMODE
Y_THRESHOLD
SELFCLOCK
RESERVED
CUR_Y(12)
START_Y
27
HBE INT enable
WIDTH
U_DELTA(16)
Y_DELTA(16)
SLEEPLESS
23
HBE (highway bandwidth error)
SC (Sampling conventions)
Y_BASE_ADR
U_BASE_ADR
V_BASE_ADR
THRESHOLD interrupt mechanism works regardless of
CAPTURE ENABLE. Hence, it can also be used to skip
a desired number of fields without constant DSPCPU
polling of VI_STATUS.
(SOURCE 9) to the PNX1300 Vectored Interrupt Control-
ler. The interrupt handler routine should check the STA-
TUS register to determine the set of VI events associated
with the request. The vectored interrupt controller should
always be set to have VI (SOURCE 9) operate in level
sensitive mode. This ensures that each event is handled.
VI asserts the interrupt request line as long as one or
more enabled events are asserted. The interrupt handler
clears one or more selected events by writing a ‘1’ to the
corresponding ACK field in VI_CTL. The clearing of the
last event leads to immediate (next DSPCPU clock edge)
de-assertion of the interrupt request line to the Vectored
Interrupt Controller. See
(Maskable and Non-Maskable Interrupts),”
tion on how to program interrupt handler routines.
0 ⇒ Co-sited
1 ⇒ Interspersed
Capture enable
19
Threshold reached
Little endian
CUR_X(12)
START_X
15
HEIGHT
DIVIDER
Threshold reached
11
MODE
Capture complete
FIELD2
Section 3.5.3, “INT and NMI
V_DELTA(16)
Philips Semiconductors
Capture complete
Threshold reached ACK
INT enable
INT enable
Capture complete ACK
(write ‘1’ to ACK)
7
0
0
0
0
0
0
0
0
0
3
for informa-
0
0
0
0
0
0
0
0
0
0