PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 225

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

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Philips Semiconductors
Table 14-4. FSSR codes for vertical filtering.
14.5.8.1
A window may start and/or end at the edge of the input
image. In this case, the two start and/or end lines needed
for the first and last lines of the window, respectively, are
missing. These pixels are supplied by the mirror multi-
plexer at the 5-tap filter which mirrors the input lines.The
mirror multiplexer is controlled by the mirror counter and
mirror end register in the same manner as in horizontal
filtering. The mirror register in vertical filtering is incre-
mented by the output line counter. Mirroring is performed
on the first two and last two lines of the column. Mirroring
is optional, depending on whether the start or end of the
line is on a window boundary. The DSPCPU or micropro-
gram must detect this and enable start and/or end mirror-
ing as required.
14.5.8.2
Figure 14-15
between the SDRAM and the filter for a scaling factor of
1.0. The bus block reads and writes require one fourth of
the filter processing time because the filter processes
data at 100 Mpix/sec, and the SDRAM reads and writes
blocks of pixels at 400 Mpix/sec (peak). The vertical filter
starts by reading in the five blocks necessary to generate
the next output block. While the current block is being
processed, the next block is read from SDRAM to pre-
pare for the next output block.
14.5.9
Figure 14-16
horizontal scaling to RGB output algorithm implementa-
tion. The six input block buffers are arranged as three
block FIFOs, one each for Y, U and V pixel streams.
These three streams are sequentially filtered, pixel by
pixel by the 5-tap filter to generate a scaled output se-
quence of Y, U, V, Y, U, V, etc. This YUV stream is fed
Figure 14-15. SDRAM and vertical filter block timing
SDRAM Bus
Filter Action
Case
1
2
3
4
5
6
Pn-2
Horizontal Scaling and Filtering for
RGB Output
5
0
1
2
3
4
Mirroring lines at the ends of an
image
Vertical filter SDRAM block timing
shows a data flow block diagram of the ICP
shows a timing diagram for block data flow
Read Y5
Pn-1
4
5
0
1
2
3
Pn+0
Read Y6
3
4
5
0
1
2
Pn+1
2
3
4
5
0
1
Filter Y2-5 => Ya
Pn+2
1
2
3
4
5
0
IO Block
0
1
2
3
4
5
Write Ya
to the YUV to RGB converter where it is converted to one
of several RGB output formats, blended with RGB over-
lay pixels supplied by the Overlay FIFO and masked by
bit mask pixels from the bit mask block. The resulting
scaled, converted, overlay blended and masked RGB
stream is sent to the PCI interface -- typically to an RGB
format frame buffer on the PCI bus -- or to SDRAM.
The input pixel streams from the input FIFOs are trans-
ferred sequentially to the 5-tap filter. Each stream has its
own set of four-stage delay registers used to perform
horizontal filtering on the stream. A pair of 3-way multi-
plexers switch the five filter data inputs and the 5-bit filter
coefficient select codes to the 5-tap filter. This set of mul-
tiplexers is driven by the YUV Sequence counter, a 2-bit
counter that provides the YUV processing sequence.
In horizontal scaling and filtering from SDRAM to
SDRAM, each Y, U and V component is filtered sepa-
rately as a complete image. In RGB output horizontal
scaling and filtering, the image is processed as three in-
terwoven streams of all three YUV components.
In the RGB output mode, the ICP normally generates
RGB data and writes it into a frame buffer memory on the
PCI bus or to the SDRAM. The frame buffer memory for-
mat is RGB with one R, one G and one B value per pixel.
This could be called RGB 4:4:4. To generate this image,
the ICP generates a YUV 4:4:4 image and converts it to
RGB. This process is done one RGB output pixel at a
time. The ICP generates a U pixel and saves it in a reg-
ister, generates a V pixel and saves it in a register, then
generates a Y pixel for output. The YUV to RGB convert-
er combines each Y pixel as it is generated with the pre-
viously stored U and V pixels to generate the RGB output
data. This process is repeated until the whole image has
been converted and sent to the PCI bus or SDRAM.
14.5.9.1
For RGB output formats, the YUV data must be scaled to
YUV 4:4:4 format before conversion to RGB. The YUV
data in SDRAM is typically stored in YUV 4:2:2. This
means that the U and V data must be upscaled by 2 rel-
ative to the Y data to generate the internal YUV 4:4:4 for-
mat required for RGB conversion.
For the YUV 4:2:2 output formats, the U and V data do
not need to be up scaled to 4:4:4. The YUV 4:4:4 data
would be upscaled only to be decimated back to YUV
4:2:2. For YUV 4:2:2 output, the U and V pixels are used
twice. This is done by having a half-speed mode for the
YUV Sequence Counter. In this mode, the sequence is
U0, V0, Y0, Y1, U2, V2, Y2, Y3, etc. The U and V are not
PRELIMINARY SPECIFICATION
Read Y7
Filter Y3-6 => Yb
YUV sequence counter in YUV 4:2:2
output Mode
Image Coprocessor
Write Yb
Filter Y4-7 => Yc
Read Y8
14-15