PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 146

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
• LSB first, with 1–16-bit data per channel.
• Complex serial frames of up to 512 bits/frame.
• Up to 8 channels of audio output.
Table 9-1. AO unit external signals
9-2
AO_OSCLK
AO_SCK
AO_WS
AO_SD1
AO_SD2
AO_SD3
AO_SD4
Signal
AO_WS, left & right data in a frame).
Type
OUT
OUT
OUT
OUT
OUT
IO
IO
Over sampling clock. Can be pro-
grammed to emit any frequency up to 40
MHz, with sub-Hz resolution. Intended for
use as the 256 or 384f
clock by the external D/A conversion sub-
system.
• When AO is programmed to act as a
• When AO is programmed to act as
AO_SCK is limited to 22 MHz. The sam-
ple rate of valid samples embedded within
the serial stream is limited by the
AO_SCK maximum frequency and the
available highway bandwidth.
• When AO is programmed as the serial-
• When AO is programmed as serial-
AO_WS is the word-select or frame-sync
signal from/to the external D/A sub-
system. Each audio channel receives 1
sample for every WS period.
AO_WS can be set to change on
AO_OSCLK positive or negative edges by
the CLOCK_EDGE bit.
Serial data to stereo external audio D/A
subsystem. AO_SD1 can be set to
change on AO_OSCLK positive or nega-
tive edges by the CLOCK_EDGE bit.
Serial data to stereo external audio D/A
subsystem. AO_SD2 can be set to
change on AO_OSCLK positive or nega-
tive edges by the CLOCK_EDGE bit.
Serial data to stereo external audio D/A
subsystem. AO_SD3 can be set to
change on AO_OSCLK positive or nega-
tive edges by the CLOCK_EDGE bit.
Serial data to stereo external audio D/A
subsystem. AO_SD4 can be set to
change on AO_OSCLK positive or nega-
tive edges by the CLOCK_EDGE bit.
serial interface timing slave (RESET
default), AO_SCK acts as input. It
receives the serial clock from the exter-
nal audio D/A subsystem. The clock is
treated as fully asynchronous to the
PNX1300 main clock.
serial interface timing master,
AO_SCK acts as output. It drives the
serial clock for the external audio D/A
subsystem. Clock frequency is a pro-
grammable integral divide of the
AO_OSCLK frequency.
interface timing slave (RESET default),
AO_WS acts as an input. AO_WS is
sampled on the opposite AO_SCK
edge at which AO_SDx are asserted.
interface timing master, AO_WS acts
as an output. AO_WS is asserted on
the same AO_SCK edge as AO_SDx.
PRELIMINARY SPECIFICATION
Description
s
oversampling
9.3
The AO unit consists of three major subsystems, a pro-
grammable sample clock generator, a DMA engine and
a data serializer.
The DMA engine reads 16 or 32-bit samples from mem-
ory using a double buffered DMA approach. The
DSPCPU initially assigns two full sample buffers contain-
ing an integral number of samples for all active channels.
The DMA engine retrieves samples from the first buffer
until exhausted and continues from the second buffer,
while requesting a new first sample buffer from the
DSPCPU, etc.
The samples are given to the data serializer, which
sends them out in a MSB first or LSB first serial frame for-
mat that can also contain 1 or 2 codec control words of
up to 16 bits. The frame structure is highly programmable
by a series of MMIO fields.
SUMMARY OF OPERATION
Philips Semiconductors