PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 83

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Cache Architecture
5.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
The high-performance video and audio throughput of
PNX1300 is implemented by its DSPCPU and autono-
mous I/O and co-processing units, but the foundation of
this processing is the PNX1300 memory hierarchy. To
get the full potential of the chip’s processing units, the
memory hierarchy must read and write data (and DSP
CPU instructions) fast enough to keep the units busy.
To meet the requirements of its target applications,
PNX1300’s memory hierarchy must satisfy the conflict-
ing goals of low cost, simple system design (e.g., low
parts count), and high performance. Since multimedia
video streams can require relatively large temporary
storage, a significant amount of external DRAM is re-
quired. Minimizing the cost of bulk memory is important.
PNX1300’s memory system achieves a good compro-
mise between cost and performance by coupling sub-
stantial on-chip caches with a glueless interface to syn-
chronous DRAM (SDRAM). SDRAM provides higher
bandwidth than standard DRAM for only a small cost pre-
mium. A block diagram of the memory system is shown
in
rower and simpler interface than would be required to
achieve similar performance with standard DRAM.
Figure 5-1. The main components of the PNX1300 memory system.
Figure
MEMORY SYSTEM OVERVIEW
5-1. SDRAM permits PNX1300 to use a nar-
VLIW
CPU
224 bits of decompressed
instruction
Two sets, each has a guard,
opcode, data, and two
address components
Three sets, each has address,
opcode, condition, and guard
Decompressor
Memory
Branch
Three
Units
Units
Two
32KB, 8-way
16KB, 8-way
Instruction
Cache
Cache
Data
The separate on-chip data and instruction caches serve
only the DSPCPU since the data access patterns of the
autonomous I/O and graphics units exhibit little or no lo-
cality of reference (they access each piece of the multi-
media data stream only once in each operation).
Without the caches, the CPU would not be able to
achieve its performance potential. SDRAM has enough
bandwidth to handle serial streams of multimedia data,
but its bandwidth and latency are insufficient to satisfy
the CPU’s high rate of random data accesses and re-
peated instruction accesses.
Table 5-1. 100-MHz PNX1300 memory bandwidth
parameters
Table 5-1
DSPCPU and the main-memory interface. Although 400
MB/s is a lot of bandwidth, it is clear that the SDRAM
alone cannot keep up with the CPU’s maximum require-
ments for instructions and data. Luckily, multimedia algo-
rithms resemble other computer programs in terms of lo-
cality of reference, so the on-chip caches typically supply
To on-chip
peripherals
PRELIMINARY SPECIFICATION
2800 MB/s
800 MB/s
400 MB/s
Magnitude
Internal data highway:
32-bit address, 32-bit
data
shows bandwidth parameters for the PNX1300
Interface
Memory
Main
Instruction bandwidth (224 bits/instruction)
Data bandwidth (two 32-bit memory ports)
Main-memory bandwidth (one 32-bit port)
Chapter 5
Use
Main-memory bus:
glueless, SDRAM
control with 32-bit
data
by Eino Jacobs
Memory
SDRAM
Main
5-1