PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 258

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
A detailed description of the configuration of the receiver
can be found in the SSI_CTL and SSI_CSR register de-
scription
SSI_RxDR is a 32-bit MMIO receive data register.
Due to the possibility of speculative reading of the
SSI_RxDR, the read itself can not be implemented to ac-
knowledge the data as a side effect. For this reason an
explicit acknowledge mechanism is provided by the
SSI_RxACK register.
The SSI_RxACK is a 1-bit MMIO register that is used to
signal the SSI receiver state machine that a word has
been successfully read from the SSI_RxDR.
17-4
Figure 17-4. The Sync Serial Interface Transmit Block Diagram
Figure 17-5. The SSI receive block diagram
SSI_RxDATA
(17.10.1
SSI_TxDATA
SSI_RxCLK
SSI_RxFSX
and 17.10.2)
PRELIMINARY SPECIFICATION
TxCLK
TxFSX
Shift Reg
Shift Reg
Receive
Transmit
RxSR
TxSR
Writing a ‘1’ to this register initiates updating of the inter-
nal state. Writing a ‘0’ has no effect.
The register cannot be read, its effect may be observed
in the WAR field of the SSI_CSR.
The status fields of the SSI_CSR will update within 1
highway clock cycle after writing to the SSI_RXACK reg-
ister.
64-byte Receive Buffer
64-byte Transmit Buffer
Receive Control Logic
Transmit Control Logic
Status Reg
Status Reg
Transmit
Receive
Philips Semiconductors
Control Reg
SSI_RXDR
Control Reg
SSI_TXDR
Data Reg
Data Reg
Receive
Receive
Transmit
Transmit