PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 139

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
clock system DDS is used to provide a single master A/
D and D/A clock. The AO unit, or the D/A converter, can
be used as serial interface timing master, and the AI unit
is set to be slave to the serial frame determined by AO
(AI SER_MASTER=0, AI_SCK and AI_WS externally
wired to the corresponding AO pins). In such systems, in-
dependent software control over A/D and D/A sampling
rate is not possible, but component count is minimized.
Table 8-3. Sample rate settings (f
MHz, improved PNX1300 mode)
Table 8-4.AI MMIO clock & interface control bits
8.5
The AI unit can accept data in a wide variety of serial
data framing conventions.
tion
CLOCK_EDGE=0, a frame is defined with respect to the
positive transition of the AI_WS signal, as observed by a
positive clock transition on AI_SCK. Each data bit sam-
pled on positive AI_SCK transitions has a specific bit po-
sition: the data bit sampled on the clock edge after the
clock edge on which the AI_WS transition is seen has bit
position 0. Each subsequent clock edge defines a new
bit position. As defined in
Figure 8-2. AI serial frame and bit position definition (POLARITY=1, CLOCK_EDGE=0).
SER_MASTER
FREQUENCY
SCKDIV
WSDIV
AI_SCK
44.1 kHz
48.0 kHz
44.1 kHz
48.0 kHz
AI_WS
AI_SD
Field Name
f
s
of
SERIAL DATA FRAMING
a
OSCLK
serial
0
256f
256f
384f
384f
1
0 ⇒ (RESET default), the A/D converter
is the timing master over the serial inter-
face. AI_SCK and AI_WS are set to be
inputs.
1 ⇒ PNX1300 is timing master over the
AI serial interface. The AI_SCK and
AI_WS pins are set to be outputs.
AI_OSCLK output. RESET default 0.
Sets the divider used to derive AI_SCK
from AI_OSCLK. Set to 0..255, for divi-
sion by 1..256. RESET default 0.
Sets the divider used to derive AI_WS
from AI_SCK. Set to 0..511 for a serial
frame length of 1..512. RESET default 0.
Sets the clock frequency emitted by the
s
s
s
s
2
frame.
3
SCK
64f
64f
64f
64f
4
Table
Figure 8-2
s
s
s
s
5
6
Description
If
FREQUENCY
8-5, other combinations
2187991971
2191574340
2208246133
2213619686
7
DSPCPUCLK
8
POLARITY=1
9
illustrates the no-
10
11
12
=133
SCKDIV
13
3
3
5
5
14
and
15
16
17
frame
18
of POLARITY and CLOCK_EDGE can be used to define
a variety of serial frame bitposition definitions.
The capturing of samples is governed by FRAMEMODE.
If FRAMEMODE=00, every serial frame results in one
sample from the serial-parallel converter. A sample is de-
fined as a left/right pair in stereo modes or a single left
channel value in mono modes. If FRAMEMODE=1y, the
serial frame data bit in bit position VALIDPOS is exam-
ined. If it has value ‘y’, a sample is taken from the data
stream (the valid bit is allowed to precede or follow the
left or right channel data provided it is in the same serial
frame as the data).
The left and right sample data can be in a LSB-first or
MSB-first form, at an arbitrary bit position, and with an ar-
bitrary length.
Table 8-5. AI MMIO serial framing control fields
PRELIMINARY SPECIFICATION
POLARITY
FRAMEMODE
VALIDPOS
LEFTPOS
RIGHTPOS
DATAMODE
SSPOS
19
Field Name
n
20
21
22
23
24
0 ⇒ serial frame starts on AI_WS negedge
(RESET default)
1 ⇒ serial frame starts on AI_WS posedge
00 ⇒ accept a sample every serial frame
(RESET default)
01 ⇒ unused, reserved
10 ⇒ accept sample if valid bit = 0
11 ⇒ accept sample if valid bit = 1
• Defines the bit position within a serial frame
• Default 0.
• Defines the bit position within a serial frame
• Default 0.
• Defines the bit position within a serial frame
• Default 0.
0 ⇒ MSB first (RESET default)
1 ⇒ LSB first
• Start/Stop bit position. Default 0.
• If DATAMODE=MSB first, SSPOS deter-
• If DATAMODE=LSB first, SSPOS deter-
25
where the valid bit is found.
where the first data bit of the left channel is
found.
where the first data bit of the right channel
is found.
mines the bit index (0..15) in the parallel
word of the last data bit. Bits 15 (MSB) up
to/including SSPOS are taken in order from
the serial frame data. All other bits are set
to ‘0’.
mines the bit index (0..15) in the parallel
word of the first data bit. Bits SSPOS up to/
including 15 are taken in order from the
serial frame data. All other bits are set to ‘0’.
26
27
28
29
30
Description
31
0
1
2
3
frame
Audio In
4
n+1
5
6
8-3
7