PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 188

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Table 12-11. 16-bit Address Mapping
PNX1300/01/02/11 Data Book
The rank is selected via the chip select bits,
MM_CS#[3:0].
The column “Row Address/H.Way Bits” specifies which
internal data-highway address bits map to the SDRAM
row address. “Row Address/Pins” specifies which lines
of PNX1300’s MM_A address bus serve as the SDRAM
row address. For the 32 MB ranksize the chip selects
may be used as row address.
The column ‘Column Address/H.Way Bits’ specifies
which data-highway address bits map to the SDRAM col-
umn address. ‘Column Address/Pins’ specifies which
lines of PNX1300’s MM_A address bus serve as the
SDRAM column address. For the 32 MB ranksize the
chip selects may be used as column address.
MM_A[12] is only defined for a 8- or 16-MB rank size.
MM_A[12] contains H.Way bit 11 during the RAS and
CAS operations. MM_A[12] can be used as a bank select
(4-bank SDRAMs) or as a Row address (two bank
SDRAMs).
MM_A[13] is only defined for a 16-MB rank size.
MM_A[13] contains H.Way bit 12 during the RAS opera-
tion. MM_A[13] can only be used as a Row address.
For the 32 MB ranksize the chip selects MM_CS#[3:2]
pins are used as addresses. MM_CS#2 is used as a
bank select in addition to MM_A[11] and MM_CS#3 is
used as a row address.
Highway address bits 5–0 are the offset within a 64-byte
block. All ‘0’ for an aligned block transfer. Table 12-8 lists
the mapping of bits 5–2 to identify in which SDRAM po-
sitions the words of a block are located. Bit 5 is always
mapped to (one of) the SDRAM internal bank selects;
thus, each SDRAM bank receives half (32 bytes) of the
block transfer.
Highway address bits 4–2 are the word offset in a cache
block. Bits 1–0 are the byte offset within a 32-bit word.
12.8.2
Table 12-11
PNX1300 data highway bus are mapped to main-memo-
ry address-bus and chip select pins (MM_A[13:0],
MM_CS#[3:2]) in 16-bit data bus mode.
12-6
Rank
2 MB
8 MB
Size
H.Way
Addr.
Rank
Bits
–
–
Address Mapping in 16-bit mode
shows how internal address bits from the
13–12,
CS#3,
CS#2,
10–0
Pins
9–0
Address
Row
20–11,5 7–0
22–13,5
H.Way
12–11,
Bits
PRELIMINARY SPECIFICATION
24,
23,
CS#3,
CS#2,
Pins
8–0
12,
Address
Column
11–6,3–1
H.Way
10–6,
Bits
3–1
24,
23,
11,
Pins
11
11
Address
Bank
H.Way
Bit
4
4
12.9
Immediately after reset, the main-memory interface is ini-
tialized by placing default values in the MM_CONFIG
and PLL_RATIOS registers (see
System
ware boot process, when PNX1300 reads initial values
from an external ROM, these registers can be set to dif-
ferent values.
After PNX1300 is released from the reset state, the
memory interface automatically executes 10 refresh op-
erations, then initializes the mode register in each
SDRAM chip.
SDRAM mode register(s).
Table 12-12. SDRAM Mode Register Settings
12.10 ON-CHIP SDRAM INTERLEAVING
The main-memory interface (MMI) takes advantage of
the on-chip interleaving of SDRAM devices. Interleaving
allows the precharge, RAS, and CAS commands needed
to access one internal bank to be performed while useful
data transfer is occurring with the other internal bank.
Thus, the overhead of preparing one bank is hidden dur-
ing data movement to or from the other.
The benefit of on-chip interleaving is sustainable full-
bandwidth data transfer (1 word per clock cycle). The
transition from one internal bank to the other happens on
8-word boundaries; transferring 8 words gives the inac-
tive bank time to prepare (perform precharge, RAS, and
CAS) so that when the last word of the 8-word block in
the active bank has been transferred, the next word from
the just-precharged bank is ready on the next cycle.
The seamless transitions between the two on-chip banks
can be sustained for a stream of contiguous addresses
with the same direction (read or write). That is, a stream
of contiguous reads or contiguous writes can sustain full
bandwidth. If a write follows a read, then a small gap be-
tween transfers is needed.
Each bank access is terminated with a read or write with
automatic precharge, making a separate precharge com-
mand before the next RAS unnecessary.
For 4 banks SDRAM devices, the signals used as bank
addresses are interchangeable (i.e. it does not matter
which of the two signals is connected to Bank 1 or Bank
0 of the SDRAM device).
12.11 REFRESH
The MMI performs SDRAM refresh cycles autonomously
using the CAS-before-RAS (CBR) mechanism. SDRAMs
have a 4K refresh interval: either 4096 rows must be re-
Burst length
Wrap type
CAS latency
MEMORY INTERFACE AND SDRAM
INITIALIZATION
Programming”). During the subsequent hard-
Parameter
Table 12-12
Philips Semiconductors
shows the settings in the
Section 12.6, “Memory
Interleaved
Value
4
3