PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 264

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Table 17-5. SSI control register (SSI_CTL) fields.
Table 17-6. IO1 mode select
Table 17-7. IO2 mode select
17-10
VSS
FMS
FSP
MOD
EMS
ILS
Bit
Bit
00
01
10
11
00
01
10
11
Field
General Purpose Output: Configures the SSI_IO1 pin for general purpose output. The pin follows the state of the WIO1
field of the SSI_CTL.
General Purpose Input: Change detector may be used. Value can be read in from the RIO1 field of the SSI_CSR.
Enable External TxCLK: Allows for use of an externally generated TxCLK. The clock is provided via the TxCLK pin. All
general purpose I/O functions are unavailable.
Disable: Pin is not used. Output buffer is tristated and the input is ignored. (RESET default)
General Purpose Output: Configures the SSI_IO2 pin as a general purpose output. The pin follows the state of the WIO2
field of the SSI_CTL.
General Purpose Input: Value can be read in from RIO2 field of the SSI_CSR.
Frame Signal TxFSX (Output): Outputs the frame signal generated by the internal frame signal generation logic.
Frame Signal TxFSX (Input): Allows for use of an externally generated TxFSX. The frame sync signal is provided via
TxFSX pin. All general purpose I/O functions are unavailable. (RESET default)
Valid Slot Size (Bit 11-8). The VSS[3:0] bits control the valid slot size (starting from slot 1) for different modem analog
front end devices. The valid setup value ranges from 1 to 16 slot(s). The value 16 is accomplished by storing a ‘0’ in
this field.
Frame Sync Mode Select (Bit 7). The FMS bit value should only be changed when the transmitter and receiver are
disabled. FMS selects the type of frame sync to be recognized by both Rx and Tx. When FMS = ‘1’, frame sync is
word-length bit clock. When this bit = ‘0’, frame sync is a 1-bit clock.
Frame Sync Polarity (Bit 6). The FSP bit value should only be changed when the transmitter and receiver are dis-
abled. FSP controls which edge of frame sync is the active edge for both Rx and Tx. This bit causes frame signal to
be active at rising edge when FSP = ‘0’ , or falling edge when FSP = ‘1’.
Mode Select (Bit 5). The MOD bit value should only be changed when the transmitter and receiver are disabled. MOD
selects the operational mode of the SSI for ISDN functionality. When MOD is set, the SSI is configured as a U-inter-
face for ISDN NT. Otherwise, set to ‘0’. Setting MOD bit and CD2 supports the MC145574 and MC145572 ISDN in-
terface transceivers.
Endian Mode Select (Bit 4). Selects the big- or little-endian mode operation. See Section
Interrupt Level Select (Bit 3-0). Sets the point where an interrupt is generated for normal data buffer servicing. The
number ranges from 1 to 15. This field controls interrupt level of both transmit and receive functions.
PRELIMINARY SPECIFICATION
Mode
Mode
Description
Philips Semiconductors
17.8
for more detail.