PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 68

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Figure 3-9. Host interrupt control register
Table 3-10. Interrupt source assignments
rent actual state of the pins. Note that the pins have neg-
ative logic (active low) polarity and are of the open
collector output type. Hence the pin voltage is low (ac-
tive) when the logical value set or seen in the INT_CTL
register is a ‘1’.
The assertion and de-assertion of host interrupts is the
responsibility of PNX1300 software.
See also
3-12
PCI INTA
PCI INTB
PCI INTC
PCI INTD
TRI_USERIRQ
TIMER1
TIMER2
TIMER3
SYSTIMER
VIDEOIN
VIDEOOUT
AUDIOIN
AUDIOOUT
ICP
VLD
SSI
PCI
IIC
JTAG
t.b.d.
SPDO
t.b.d.
HOSTCOM
APP
DEBUGGER
RTOS
SOURCE
0x10 3038
NAME
MMIO_BASE
offset:
Section 11.6.17, “INT_CTL Register.”
INT_CTL (r/w)
19..24
26..27
NUM
SRC
10
12
13
14
15
16
17
18
25
28
29
30
31
11
0
1
2
3
4
5
6
7
8
9
PRELIMINARY SPECIFICATION
level
MODE
level
level
level
level
either
edge
edge
edge
edge
level
level
level
level
level
level
level
level
level
level
edge
edge
edge
edge
PCI_INTA# pin signal
PCI_INTB# pin signal
PCI_INTC# pin signal
PCI_INTD# pin signal
external general-purpose
pin
general-purpose timer
general-purpose timer
general-purpose timer
reserved for debugger
video in block
video out block
audio in block
audio out block
image coprocessor
VLD coprocessor
SSI interface
PCI BIU (DMA, etc.; see
Table 11-14
interrupt causes)
I
JTAG interface
reserved for future devices
SPDO block
reserved for future devices
(software) host communica-
tion
(software) application
(software) debugger
(software) RTOS
2
SOURCE DESCRIPTION
C interface
31
for possible
27
23
3.7
A host CPU can generate an interrupt to PNX1300 in
several ways:
• by a PCI MMIO write to IPENDING to assert the
• by a hardware circuit that asserts one of the interrupt
The first and most common method requires no circuitry
and leaves the interrupt pins available for other purposes.
3.8
The DSPCPU contains four programmable timer/
counters, all with the same function. The first three
(TIMER1, TIMER2, TIMER3) are intended for general
use. The fourth timer/counter (SYSTIMER) is reserved
for use by the system software and should not be used
by applications.
Each timer has three registers as shown in
The MMIO register addresses shown are offset address-
es with respect to the timer’s base address.
Each timer/counter can be set to count one of the event
types
DATABREAK event is special, in that the timer/counter
may increment by zero, one or two in each clock cycle.
For all other event types, increments are by zero or one.
The CACHE1 and CACHE2 events serve as cache per-
formance monitoring support. The actual event selected
for CACHE1 and CACHE2 is determined by the
MEM_EVENTS MMIO register, see
mance Evaluation Support.”
CLK, etc.) is selected as an event, positive-going edges
on the signal are counted.
Each timer increments its value until the modulus is
reached. On the clock cycle where the incremented val-
ue would equal or exceed the modulus, the value wraps
around to zero or one (in the case of an increment by
two), and an interrupt is generated as defined in
Table
set as edge-sensitive. No software interrupt acknowl-
edge to the timer device is necessary.
Counting starts and continues as long as the run bit is
set.
Loading a new modulus does not affect the contents of
the value register. If a store operation to either the mod-
ulus or value register results in value and modulus being
the same, no interrupt will be generated. If the run bit is
set, the next value will be modulus+1 or modulus+2, and
HOSTCOMM interrupt (bit 28)
request pins TRI_USERIRQ, or INTA..INTD.
19
3-10. The timer interrupt source mode should be
HOST TO PNX1300 INTERRUPTS
TIMERS
specified
IS[D:A]
15
in
IE[D:A]
Table
11
Philips Semiconductors
If a PNX1300 pin signal (VI-
INT[D:A]
3-12.
7
Section 5.7, “Perfor-
Note
Figure
3
that
3-10.
0
the