PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 180

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Table 11-21. PNX1300 PCI commands as target
Figure 11-10. Basic single-data-phase read opera-
come a PCI-bus initiator, i.e., only the DSPCPU and ICP
can access external resources.
11.7.1
When the DSPCPU reads or writes PC memory, the PCI
transaction has only a single data phase. A typical sin-
gle-data-phase
Figure
asserts the frame# signal to indicate that the transaction
has begun and that an address and command are stable
on ad and c/be#, respectively.
PNX1300 then releases the ad bus, deasserts frame#,
asserts irdy#, asserts byte enables on c/be#, and waits
for the target to claim the transaction by asserting
devsel#. The target asserts trdy# to signal the master
that the ad bus contains stable data. The assertion of
trdy# causes the initiator (PNX1300 in this case) to sam-
ple the ad bus data and deassert irdy# to complete the
single-data-phase read transaction.
Figure 11-11
eration. The operation begins like a read: PNX1300 as-
serts the frame# signal and drives the ad bus with the tar-
get address and drives the command onto the c/be# bus.
The operation continues when PNX1300 deasserts
frame#, asserts irdy#, and drives the byte enables as be-
fore, but it also drives the data to be written on the ad
bus. The target device asserts devsel# to claim the trans-
action. Eventually, the target asserts trdy# to signal that
it is sampling the data on the ad bus. PNX1300 continues
11-16
Configuration read
Configuration write
Memory read
Memory write
Memory write and invalidate
Memory read line
Memory read multiple
PNX1300 Responds To
devsel#
pci_clk
frame#
c/be#
11-10. During the first clock period, the PNX1300
trdy#
irdy#
ad
Single-Data-Phase Operations
shows a typical single-data-phase write op-
1
read
Command
Address
PRELIMINARY SPECIFICATION
2
operation
Byte Enables
I/O read
I/O write
Interrupt acknowledge
Special cycle
Dual address
3
PNX1300 Ignores
is
Data
4
illustrated
in
Figure 11-11. Basic single-data-phase write opera-
to drive the data on the ad bus until after the target deas-
serts trdy#, which completes the write operation.
11.7.2
As with the single-data-phase operations, DMA opera-
tions begin with the assertion of frame# and valid ad-
dress and command information. See
target knows a burst is requested because frame# re-
mains asserted when irdy# becomes asserted.
In the example timing of
ceiving the burst from PNX1300. The target asserts
devsel# and trdy# simultaneously. The trdy# signal re-
mains asserted while PNX1300 sends a new word of
data on each PCI clock cycle. The burst operation shown
is a 16-word burst transfer. Since only the starting ad-
dress is sent by the initiator, both initiator and target must
increment source and destination addresses during the
burst.
The initiator signals the end of the burst of data in
Figure 11-12
last word (or partial word) of data is transferred in the
clock cycle after frame# is deasserted. Finally, the target
acknowledges the last data phase by deasserting trdy#
and devsel#.
Figure 11-13
transfers. The ICP is capable of exploiting the high band-
width available with back-to-back DMA operations when
it is writing image data to a frame buffer on a PCI video
card.
The timing of
granted to PNX1300 until at least the beginning of the
second DMA burst operation. For as long as bus owner-
ship is granted to PNX1300 and the ICP has queued re-
quests for data transfer, the PCI interface will perform
back-to-back DMA operations. If the target eventually
becomes unable to accept more data, it signals a discon-
nect on the PNX1300 PCI interface. The PCI interface
remembers where the DMA burst was interrupted and at-
tempts to restart from that point after two bus clocks.
devsel#
frame#
pci_clk
c/be#
irdy#
trdy#
ad
Multi-Data-Phase Operations
when it deasserts frame# in clock 17. The
1
Figure 11-13
illustrates back-to-back DMA burst data
Command
Address
2
Figure
Philips Semiconductors
assumes that the PCI bus is
3
11-12, a fast device is re-
Byte Enables
Data
Figure
11-12. The
n