PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 88

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
5.3.10
A program can exercise some control over the operation
of the data cache by executing special operations. The
special operations can cause the data cache to initiate
the copyback or invalidation of a block in the cache.
These operations are typically used by software to keep
the cache coherent with main memory.
In addition, there are special operations that allow a pro-
gram to read tag and status information from the data
cache.
Special data cache operations are always executed on
the memory port associated with issue slot 5.
5.3.10.1
The data cache controller recognizes a copyback and an
invalidate operation as shown in
Table 5-7. Copyback and invalidate operations
The dcb and dinvalid operations both compute a target
word address that is the sum of a register and seven-bit
offset. The offset can be in the range [–256..252] and
must be divisible by four.
dcb operation. The dcb operation computes the target
address, and if the block containing the address is found
in the data cache, its contents are written back to main
memory if the block is both valid and dirty. If the block is
not present, not valid, or not dirty, no action results from
the dcb operation. If the dcb causes a copyback to occur,
the CPU is stalled until the copyback completes. If the
block is not in cache, the operation causes no stall cy-
cles. If the block is in cache but not dirty, the operation
causes 4 stall cycles. If the block is dirty, the dcb opera-
tion causes a writeback and takes at least 19 stall cycles.
The dcb operation clears the dirty bit but leaves a valid
copy of the written-back block in the cache.
dinvalid operation. The dinvalid operation computes
the target address, and if the block containing the ad-
dress is found in the data cache, its valid and dirty bits
Figure 5-7. Result formats for rdtag and rdstatus operations.
5-6
dcb(offset) rsrc1
dinvalid(offset) rsrc1
Mnemonic
rdstatus Result Format
Special Data Cache Operations
rdtag Result Format
Copyback and invalidate operations
Data-cache copyback block. Causes
the block that contains the target
address to be copied back to main
memory if the block is valid and dirty.
Data-cache invalidate block. Causes
the block that contains the target
address to be invalidated. No copy-
back occurs even if the block is dirty.
PRELIMINARY SPECIFICATION
31
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
Table
Description
5-7.
27
23
0 0 0
VALID
19
are cleared. No copyback operation will occur even if the
block is valid and dirty prior to executing the dinvalid op-
eration. The CPU is stalled for 2 cycles, if the target block
is in the cache; otherwise, no stall cycles occur.
A dinvalid or dcb operation updates the LRU information
to least recently used in its set.
Programmer’s note: Software should not execute din-
valid operations on locked blocks; otherwise, a ‘hole’ is
created that cannot be reused until locking is deactivated.
5.3.10.2
The data cache controller recognizes two DSPCPU op-
erations for reading cache status as shown in
The rdtag and rdstatus operations both compute a target
word address that is the sum of a register and scaled
seven-bit offset. The offset must be divisible by four and
in the range [–256..252].
Table 5-8. Cache read-status operations
rdtag operation. The target address computed by rdtag
selects the data cache block by specifying the cache set
and set element directly. Address bits [10..6] specify the
cache set (one of 32), and bits [13..11] specify the set el-
ement (one of eight). All other target address bits are ig-
nored. This operation causes no CPU stall cycles.
The result of the rdtag operation is a full 32-bit word with
the format shown in
rdstatus operation. The target address computed by rd-
status selects the data cache set by specifying the set
number directly. Address bits [10..6] specify the cache
set (one of 32); all other target address bits are ignored.
This operation causes 1 CPU stall cycle.
The result of the rdstatus operation is a full 32-bit word
with the format shown in
“LRU Bit Definitions,”
rdtag(offset) rsrc1
rdstatus(offset) rsrc1
Mnemonic
15
DIRTY
Data cache tag and status
operations
11
TAG
Figure
Read data-cache tag. The target
address selects a data-cache block
directly; the operation returns a 32-bit
result containing the 21-bit cache tag
and the valid bit.
Read data-cache status. The target
address selects a data-cache set
directly; the operation returns a 32-bit
result containing the set’s eight dirty
bits and ten LRU bits.
for a description of the LRU bits.
Figure
Philips Semiconductors
5-7.
7
Description
5-7. See
LRU
3
Section 5.6.7,
0
Table
5-8.