PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 277

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Figure 20-4
which double weight is given to requester A.
Figure 20-5. Arbitration architecture
Figure 20-4. State diagram of round robin arbitra-
tor with 3 requesters; A has double weight.
L1 arbitration
Cache priority-based arbitration
ic_req
1/2/3
A1
C
1
A
dc_req
shows a state machine with 3 requesters in
L2 arbitration
dc_mmio_req
vo_req
1/3/5
A&~B
1
B&~A
1
B
L3 arbitration
dc_req_pref
A&~C
C
icp_reqh
icp_reql
1/3/5/7
C&~A
1
1/2/3
A
L4 arbitration
vi_req
A2
1/3/5/7
B
1/2
pci_mmio_req
pci_req
L5 arbitration
1/3/5
1/3/5
vld_req
Such state machines can become very complex and
cannot be implemented for a large system like PNX1300
with 9 requesters. Hierarchy or arbitration levels are
used to overcome this problem.
20.3.2
The arbitration is split into multiple levels of hierarchy.
Each level of hierarchy has an independent arbitration
state machine. At the bottom of the hierarchy, the arbitra-
tion is performed between a group of units. Whichever of
these units ‘wins’ is passed to the next level of hierarchy,
where the selected unit competes with other units at that
level for highway access.This is continued until the high-
est level of arbitration.
By splitting arbitration into multiple levels it is easy to
support a large number of highway units while the com-
plexity of the arbitration state machines at each level of
hierarchy remains modest.
PRELIMINARY SPECIFICATION
L6 arbitration
2
1/3/5
ai_req ao_req
Arbitration Levels
1
bti_mmio_req
1
1/2
bti_req
1
dvdd_req
1
spdo_req
1
Arbiter
20-3