PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 141

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
ting of the LITTLE_ENDIAN bit in the AI_CTL register de-
termines how increasing memory addresses map to byte
positions within words. Refer to
for details on byte ordering conventions.
The AI hardware implements a double buffering scheme
to ensure that no samples are lost, even if the DSPCPU
is highly loaded and slow to respond to interrupts. The
DSPCPU software assigns buffers by writing a base ad-
dress and size to the MMIO control fields described in
Table
software synchronization.
In 8-bit capture modes, the eight MSBs of the serial par-
allel converter output data are written to memory. In 16-
bit capture modes, all bits of the parallel data are written
to memory. If SIGN_CONVERT is set to ’1’, the MSB of
the data is inverted, which is equivalent to translating
from two’s complement to offset binary representation.
This allows the use of an external two’s complement 16-
bit A/D converter to generate 8-bit unsigned samples,
which is often used in PC audio.
Note that the AI hardware does not generate A-law or µ-
law 8-bit data formats. If such formats are desired, the
DSPCPU can be used to convert from 16-bit linear data
to A-law or µ-law data.
Figure 8-5. AI status/control field MMIO layout.
MMIO_base
0x10 1C0C
0x10 1C1C
0x10 1C00
0x10 1C04
0x10 1C08
0x10 1C10
0x10 1C14
0x10 1C18
8-7. Refer to
offset:
AI_STATUS (r/w)
AI_CTL (r/w)
AI_SERIAL (r/w)
AI_FRAMING (r/w)
AI_FREQ (r/w)
AI_BASE1 (r/w)
AI_BASE2 (r/w)
AI_SIZE (r/w)
Section 8.7
SER_MASTER
CAP_ENABLE
POLARITY
DATAMODE
RESET
FRAMEMODE
SIGN_CONVERT
Appendix C, “Endian-ness,”
for details on hardware/
CAP_MODE
CLOCK_EDGE
LITTLE_ENDIAN
31
31
31
31
31
DIAGMODE
SLEEPLESS
VALIDPOS
27
27
27
27
27
23
23
23
23
23
Table 8-7. AI MMIO DMA control fields
PRELIMINARY SPECIFICATION
LITTLE_ENDIAN
BASE1
BASE2
SIZE
CAP_MODE
SIGN_CONVERT
Field Name
BASE1
BASE2
19
19
19
19
19
LEFTPOS
SIZE (in samples)
FREQUENCY
0 ⇒ capture in big endian memory format
(RESET default)
1 ⇒ capture little endian
Base address of buffer1; a 64-byte
aligned address in local SDRAM.
RESET default 0.
Base address of buffer2; a 64-byte
aligned address in local SDRAM.
RESET default 0.
• Number of samples to be placed in
• Stereo modes: a pair of 8- or 16-bit data
• Mono modes: a single value is 1 sample
• RESET default 0.
00 ⇒ mono (left ADC only), 8 bits/sample.
(RESET default).
01 ⇒ stereo, 2 times 8 bits/sample
10 ⇒ mono (left ADC only), 16 bits/sample
11 ⇒ stereo, 2 times 16 bits/sample
0 ⇒ leave MSB unchanged (RESET
default)
1 ⇒ invert MSB
15
15
15
15
15
buffer before switching to other buffer
is 1 sample
RESERVED
HBE (Highway bandwidth error)
WSDIV
OVR_INTEN
HBE_INTEN
11
BUF2_INTEN
11
11
11
11
BUF1_ACTIVE
BUF1_INTEN
Description
RIGHTPOS
OVERRUN
ACK_OVR
ACK_HBE
7
7
7
7
7
BUF2_FULL
BUF1_FULL
0
0
0
SCKDIV
ACK2
0
0
0
ACK1
Audio In
0
0
0
3
3
3
3
3
SSPOS
0
0
0
0
0
0
8-5
0
0
0
0
0
0
0
0