PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 361

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
fsubflags
SYNTAX
FUNCTION
DESCRIPTION
rsrc2 and writes a bit vector representing the exception flags into rdest. The argument values are in IEEE single-
precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as
the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. Rounding is
according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before
computing the difference, and the IFZ bit in the result is set. If the difference would be denormalized, the OFZ bit in the
result is set.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-63
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x0080000 (1.175494351e-38)
r84 = 0x7f800000 (+INF),
r85 = 0x7f800000 (+INF)
r70 = 0x7f7fffff (3.402823466e+38)
r86 = 0xff7fffff (-3.402823466e+38)
r87 = 0xffffffff (QNaN))
r30 = 0x3f800000 (1.0
r87 = 0xffbfffff (SNaN))
r30 = 0x3f800000 (1.0
r83 = 0x0080001 (1.175494421e-38),
r89 = 0x0080000 (1.175494351e-38)
The
The
[ IF rguard ] fsubflags rsrc1 rsrc2 → rdest
if rguard then
fsubflags
fsubflags
rdest ← ieee_flags((float)rsrc1 – (float)rsrc2)
31
0
Initial Values
operation computes the IEEE exceptions that would result from computing the difference rsrc1–
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
PRELIMINARY SPECIFICATION
fsubflags r60 r30 → r90
fsubflags r40 r60 → r95
IF r10 fsubflags r40 r80 → r100
IF r20 fsubflags r40 r80 → r110
fsubflags r40 r81 → r111
fsubflags r82 r83 → r112
fsubflags r84 r85 → r113
fsubflags r70 r86 → r120
fsubflags r87 r30 → r125
fsubflags r87 r30 → r125
fsubflags r83 r89 → r126
IEEE status flags from floating-point subtract
Operation
7
0
OFZ
6
IFZ
5
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
fsub faddflags readpcsw
r90 ← 0
r95 ← 0
no change, since guard is false
r110 ← 0x2 (INX)
r111 ← 0x20 (IFZ)
r112 ← 0x40 (OFZ)
r113 ← 0x10 (INV)
r120 ← 0xA (OVF,INX)
r125 ← 0x0
r125 ← 0x10 (INV)
r126 ← 0x4 (UNF)
OVF
3
Philips Semiconductors
UNF
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
1, 4
falu
114
No
—
2
3