PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 342

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Floating-point compare equal
SYNTAX
FUNCTION
DESCRIPTION
argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point values;
the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing the
comparison, and the IFZ flag in the PCSW is set. If
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point operation but can only be reset by an explicit
occurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at the
same time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
r30 = 0x40400000 (3.0)
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
r50 = 0x7f800000 (+INF)
The
The
The
[ IF rguard ] feql rsrc1 rsrc2 → rdest
if rguard then {
}
if (float)rsrc1 = (float)rsrc2 then
else
feqlflags
feql
feql
rdest ← 1
rdest ← 0
Initial Values
operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is equal to the second
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the exception flags that would result from an individual
feql r30 r40 → r80
feql r30 r30 → r90
IF r10 feql r60 r30 → r100
IF r20 feql r60 r30 → r110
feql r30 r60 → r120
feql r30 r61 → r121
feql r50 r55 → r125
feql r60 r65 → r126
feql r50 r50 → r127
writepcsw
Operation
feql
causes an IEEE exception, the corresponding exception
PRELIMINARY SPECIFICATION
operation. The update of the PCSW exception flags
PNX1300/01/02/11 DSPCPU Operations
r80 ← 0
r90 ← 1
no change, since guard is false
r110 ← 0
r120 ← 0
r121 ← 0
r125 ← 0
r126 ← 0, IFZ flag set
r127 ← 1
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ieql feqlflags fneq
readpcsw writepcsw
ATTRIBUTES
SEE ALSO
Result
feql
.
fcomp
feql
148
No
—
2
1
3
A-44