PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 168

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
I/O (I/O access enable). This bit controls a device’s abil-
ity to respond to I/O-space accesses. A value of ’0’ dis-
ables PCI device response; a value of ’1’enables re-
sponse. This bit is hardwired to ’0’ because all PNX1300
internal registers are memory mapped.
Figure 11-3. Command Register format.
11-4
Figure 11-2. PCI configuration header region register layout and initial values. (All values in hex.)
Command Register
31
0
0
0
0
p
p
0
0
s
0
0
0
0
1
1
0
0
0
p
p
0
0
s
0
0
0
Normally ’0’
Normally one
Max_Lat (0x01)
BIST (0x00)
0
0
0
0
p
p
0
0
s
0
0
0
1
0
0
0
0
p
p
0
0
s
0
0
0
0
0
0
p
p
0
0
s
0
0
0
Device ID (0x5402)
sp sp
1
0
1
0
p
0
0
s
0
0
0
PRELIMINARY SPECIFICATION
Subsystem ID
0
1
0
1
0
0
p
0
0
s
0
0
0
15
Status
Hardwired to ground
Hardwired to V
sp
0
0
0
0
p
0
0
s
0
0
1
sp sp sp
23
0
0
1
Class Code (0x048000)
0
p
0
0
s
0
0
0
Header Type (0x00)
0
0
0
0
p
0
0
s
0
0
0
Min_Gnt (0x03)
Reserved
0
0
0
0
p
0
0
s
0
0
0
Four other base address registers
dd
sp
Expansion Rom Base Address
0
0
0
0
0
0
s
0
0
0
0
reserved
0
0
0
0
0
0
s
0
0
0
Two reserved registers
DRAM Base Address
MMIO Base Address
Reserved register
0
0
0
0
0
0
0
s
0
0
0
sp
s
1
0
0
0
0
0
0
s
0
0
1
Key
Set by software if aperture size allows
Set by hardware from boot EEPROM
0
0
0
0
0
0
0
s
0
0
1
10
15
0
0
p
0
0
0
0
s
0
0
0
FB
Interrupt Pin (0x01)
9
0
0
p
0
0
0
0
s
0
0
0
Latency Timer
reserved
SERR#
0
0
p
0
0
0
0
s
0
0
0
8
1
0
p
0
0
0
0
s
0
0
0
MA (Memory access enable). This bit controls re-
sponse to memory-space accesses. A value of ’0’ dis-
ables PNX1300 response; a value of ’1’ enables re-
sponse. This bit is set to ’0’ at power-up; software can set
this bit to ’1’ with a configuration write.
Wait
0
0
p
0
0
0
0
s
0
0
0
Subsystem Vendor ID
7
Vendor ID (0x1131)
0
0
0
0
0
0
0
s
0
0
0
PAR
6
0
0
0
0
0
0
0
0
s
0
0
0
Command
1
1
0
0
0
0
0
0
s
0
0
1
VGA
5
Prefetchable
0
0
1
0
0
0
0
0
s
0
0
p
7
Revision ID (see text)
MWI
0
1
0
0
0
0
0
0
s
0
0
p
Cache Line Size
4
p
Interrupt Line
1
0
0
0
0
0
0
s
0
0
p
0 p
Set by software
SC
1
p
0
0
0
0
0
s
0
0
p
3
0
0
0
p
s
0
0
0
s
0
0
p
EM
Philips Semiconductors
2
0
1
0
p
0
0
0
0
s
0
0
p
0
1
1
0
0
0
0
s
0
0
p
0
MA
1
1
0
0
0
0
0
0
0
0
s
0
0
p
I/O
0
00
04
08
0C
10
14
18, 1C,
20, 24
28
2C
30
34, 38
3C