PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 318

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Read clock cycle counter, least-significant word
SYNTAX
FUNCTION
DESCRIPTION
cycles
register, rdest. The contents of the master counter are transferred to the slave CCCOUNT register only on a
successful interruptible jump and on processor reset. Thus, if
intervening interruptible jumps, the operation pair is guaranteed to be a coherent sample of the master clock-cycle
counter. The master counter increments on all cycles (processor-stall and non-stall) if PCSW.CS = 1; otherwise, the
counter increments only on non-stall cycles.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
CCCOUNT_HR = 0xabcdefff12345678
r10 = 0, CCCOUNT_HR = 0xabcdefff12345678
r20 = 1, CCCOUNT_HR = 0xabcdefff12345678
Refer to
The
[ IF rguard ] cycles → rdest
if rguard then
rdest ← CCCOUNT<31:0>
cycles
operation copies the low 32 bits of the slave register of Clock Cycle Counter (CCCOUNT) to the destination
Section 3.1.5, “CCCOUNT—Clock Cycle Counter”
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
cycles → r60
IF r10 cycles → r70
IF r20 cycles → r100
Operation
PRELIMINARY SPECIFICATION
for a description of the CCCOUNT operation. The
cycles
PNX1300/01/02/11 DSPCPU Operations
and
hicycles
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r30 ← 0x12345678
no change, since guard is false
r100 ← 0x12345678
hicycles curcycles
ATTRIBUTES
writepcsw
SEE ALSO
are executed without
Result
cycles
fcomp
154
No
—
0
1
3
A-20