PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 128

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Table 7-7. VO_CTL register fields
7.16.3
The VO-related registers and their fields are shown in
Table
Table 7-8. VO register fIelds
7-18
YTR_ACK
BFR1_INTEN
BFR2_INTEN
HBE_INTEN
URUN_INTEN
YTR_INTEN
LTL_END
VO_ENABLE
VO_CLOCK
VO_FRAME
VO_FIELD
Register
Field
7-8. Their fields are unchanged from the TM-1000,
VO-Related Registers
FREQUENCY
FRAME_LENGTH
FIELD_2_START
FRAME_PRESET
F1_VIDEO_LINE
F2_VIDEO_LINE
F1_OLAP
F2_OLAP
Acknowledge Y threshold.
Writing a ’1’ to this bit clears the YTR flag and resets its interrupt condition. YTR signals the CPU to set new point-
ers for the next field. If YTR_ACK is not received by the time the active image area for the next field starts, the
URUN flag is set. Data transfer continues with the old pointer values.
Enable interrupt conditions.
Enable corresponding interrupts to be generated when the BFR1_EMPTY, BFR2_EMPTY, HBE, URUN (under-
run/end of transfer), and YTR (end of field/buffer) flags are set, respectively.
Note: BFR2_INTEN, URUN_INTEN, YTR_INTEN must be 0 in message passing mode.
Little-endian.
Specifies that data in SDRAM is stored in little-endian format. This only affects the overlay packed-image format
interpretation in video-refresh modes. Refer to
Enable the EVO to send image data or message data to its output.
Note: This bit should not be simultaneously asserted with the RESET bit. The correct sequence to reset and
enable the EVO is as follows.
• Set all VO_CTL control fields as desired, writing VO_CTL with RESET = 1, VO_ENABLE = 0.
• Retain all desired values of control fields, but rewrite VO_CTL with RESET = 0, VO_ENABLE = 0.
• Finally, still retaining all desired control fields, rewrite VO_CTL with RESET = 0, VO_ENABLE = 1.
Setting VO_ENABLE in video-refresh modes starts the EVO sending image data beginning with the first pixel in
the image. Setting VO_ENABLE in data-streaming and message-passing modes starts the EVO sending data
beginning with the first byte in Buffer 1. In video-refresh and data-streaming modes, VO_ENABLE remains set until
cleared by the CPU. In message-passing mode, VO_ENABLE is cleared when BFR1_EMPTY is set, indicating the
end of message transfer.
Note: De-asserting VO_ENABLE in video-refresh modes causes SDRAM reads to stop, but sync framing and
BFR1_EMPTY generation and interrupts remain fully operational. The transmitted active image data is undefined
in this case. To fully halt video output, a software reset is required.
PRELIMINARY SPECIFICATION
Field
Total number of lines per frame; the ending value of the Frame Line Counter; typically 525
Start line number in the Frame Line Counter; where the second field of the frame begins.
Value loaded into the Frame Line Counter when frame timing edge is received on
VO_CLK frequency. See DDS equation in
or 625. Note: the Frame Line Counter counts from 1 to 525 or 625, consistent with
CCIR 656 line numbering.
If non-interlaced pictures are desired, then the same value is programmed for Field 1 and
Field 2. Field 1 becomes Frame 1 and Field 2 becomes Frame 2.
VO_IO2.
Line number in the Frame Line Counter of the first active video line of Field 1 of the frame.
Line number in the Frame Line Counter of the first active video line of Field 2 of the frame.
If non-interlaced pictures are desired, this is programmed to the same value as
F1_VIDEO_LINE
Overlap of the SAV and EAV codes from Field 1 to Field 2. Overlap is defined as the delay
in lines from start of blanking for Field 2 until SAV and EAV codes for Field 2 are emitted.
Typical values are +2 for 525/60 and +2 for 625/50.
Overlap in lines of the SAV and EAV code from Field 2 to Field 1. Overlap is defined as
the delay in lines from start of blanking for Field 1 until the SAV and EAV codes for Field 1
are emitted. Typical values are +3 for 525/60 and –2 for 625/50. The negative value
means Field 1 blanking actually starts two lines before end of Field 2 of previous frame.
This overlap is described in
Appendix C, “Endian-ness,”
however their function may vary depending upon the
PNX1300 features that are selectively enabled by
EVO_CTL (see
Description
Table 7-4 on page
Description
Figure
Section
7-6, and illustrated in
7-6, and PLL description in
for details on byte ordering.
7.16.4).
Philips Semiconductors
Figure
7-31.
Section
7.19.