PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 90

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
5.3.12
Load and store operations have an operation latency of
three cycles, regardless of the size of the data transfer.
5.3.13
Memory operations that reference MMIO registers are
not cached, and the CPU is stalled until the MMIO refer-
ence completes. A MMIO register reference occurs when
an address is in the range:
[MMIO_BASE] ≤ address < ([MMIO_BASE] + 0x200000)
The size of the MMIO aperture is hardwired at 2 MB.
5.3.14
Any CPU memory operation that references an address
outside the SDRAM and MMIO address apertures is as-
sumed to reference a device or memory on the PCI bus.
PCI-bus data transfers are not cached, and the CPU is
stalled until the PCI transfer completes.
5.3.15
The data cache causes the CPU to stall when:
1. Any cache miss occurs.
2. Two simultaneously issued, cacheable memory oper-
3. An access that references an address in the MMIO
4. An access to the PCI bus is issued.
5. A non-trivial copyback or invalidate operation is is-
6. An access to the non-cacheable region in the DRAM
5.3.16
When PNX1300 is reset, the data cache executes an ini-
tialization sequence. The cache asserts the CPU stall
signal while it sequentially resets all valid and dirty bits.
The cache de-asserts the stall signal after completing the
initialization sequence.
5.4
The instruction cache stores compressed CPU instruc-
tions; instructions are decompressed before being deliv-
ered to the CPU. The following sections describe the in-
struction
summarizes instruction-cache characteristics.
Figure 5-8. Format of the instruction-cache parameters register.
5-8
MMIO_BASE
ations need to access the same cache bank (bank
conflict).
aperture is issued.
sued.
aperture is issued.
0x10 0020
offset:
INSTRUCTION CACHE
PCI Bus References
CPU Stall Conditions
Operation Latency
MMIO Register References
Data Cache Initialization
cache
IC_PARAMS (r/o)
and
PRELIMINARY SPECIFICATION
its
operation;
31
Table 5-11
27
23
BLOCKSIZE
Table 5-11. Instruction cache characteristics
5.4.1
The PNX1300 instruction cache is 32 KB in size with a
64-byte block size. Thus, the cache contains 512 blocks
each with its own address tag. The cache is 8-way set-
associative, so there are 64 sets, each containing 8 tags.
A single valid bit is associated with a block, so each block
and associated address tag is either entirely valid or in-
valid; on a cache miss, 64 bytes are read from SDRAM
to make the entire block valid.
The geometry of the instruction cache is available to soft-
ware by reading the MMIO register IC_PARAMS.
Figure 5-8
Table 5-12
The product of the block size, associativity, and number
of sets gives the total cache size (32 KB in this case).
Table 5-12. IC_PARAMS field values
5.4.2
PNX1300 instruction addresses are mapped onto the
data cache storage structure as shown in
instruction address is partitioned into three fields as de-
scribed in
Cache size
Cache associativity
Block size
Valid bits
Replacement policy Hierarchical LRU (least-recently used)
Operation latency
Coherency enforce-
ment
Cache locking
BLOCKSIZE
ASSOCIATIVITY
NUMBER_OF_SETS
Characteristic
19
General Cache Parameters
Address Mapping
Table 5-13
shows the format of the IC_PARAMS register;
lists its field values.
Field Name
ASSOCIATIVITY
15
32 KB
8-way set-associative
64 bytes
One valid bit per 64-byte block
among the eight blocks in a set
Branch delay is three cycles
Software uses a special operation to
enforce cache coherency
Up to 1/2 (four out of eight blocks of
each set) of the cache contents can be
locked; granularity is 64 bytes
11
PNX1300 Implementation
Philips Semiconductors
NUMBER_OF_SETS
7
Figure
64
8
64
3
Value
5-9. An
0