PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 284

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
21.4
The sequence of events to power down PNX1300 is as
follows:
• Issue a MMIO write to the POWER_DOWN register
• The main memory interface (MMI) waits till the com-
• The MMI brings SDRAM into the self refresh state,
• All units that participate in the power down, respond
• Only the PLL, interrupt controller, timers, wake-up
• An interrupt is detected by the interrupt controller or a
• The MMI de-asserts the global_power_down signal,
• The MMI recovers SDRAM from self-refresh.
• The MMI causes completion of the MMIO operation
• When software takes an interruptible branch opera-
21.5
The register POWER_DOWN has an offset 0x100108 in
the MMIO aperture and has no content. Writing to this
21-2
Figure 21-1. Power down register BLOCK_POWER_DOWN
pletion of the current SDRAM transfer, if there is one
still busy.
goes into a wait state, and asserts the global signal
global_power_down.
to the global_power_down signal by disabling their
clocks.
logic, the PCI bus interface, and any peripherals that
have their SLEEPLESS bit control bit set continue to
be clocked. The SDRAM clock continues.
unit that didn’t participate in the power down requests
a memory transfer.
activating all blocks on the chip.
that initiated the power down sequence.
tion, the interrupt that caused the wake-up will be
serviced (if the wake-up was initiated by an interrupt).
MMIO_base
0x10 3428
DETAILED SEQUENCE OF EVENTS
FOR GLOBAL POWER DOWN
MMIO REGISTER POWER_DOWN
offset:
BLOCK_POWER_DOWN (r/w)
PRELIMINARY SPECIFICATION
31
27
23
19
register has the side-effect of powering down the chip.
Reading from this register returns an undefined value
and has no side-effect.
21.6
This feature is new in PNX1300. It selectively shuts off a
particular block or a set of blocks based on software pro-
gramming.
This type of power down can be used in applications
where certain blocks will never participate in the opera-
tion of the chip. The objective of having this type of power
down is saving on power consumption.
Each peripheral unit which can participate in the global
power down can be selectively powered down.
This is done by setting a control bit in MMIO register
BLOCK_POWER_DOWN specifically for the block. The
BLOCK_POWER_DOWN register is located at MMIO
offset 0x103428. See
Setting a particular bit to ’1’ in this register has the effect
of shutting off the corresponding block. Writing ’0’ to this
bit, enables the power for the block again.
A block should not be powered down if it is active. Enable
bit should be set to ‘0’ before deciding to power down the
block.
Note: The unassigned bits of this register have to be writ-
ten to ‘0’ and read as ‘0’.
Note: Writing to the global POWER_DOWN register (at
offset 0x100108) has no effect on the contents of the
BLOCK_POWER_DOWN register (at offset 0x103428),
and vice versa.
SPDO
15
DVDD
BLOCK POWER DOWN
11
SSI
Figure 21-1
VLD
ICP
Philips Semiconductors
AO
below.
AI
EVO
VI
3
0