PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 143

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Note that the buffers must be 64-byte aligned, and a mul-
tiple of 64 samples in size (the six LSBs of AI_BASE1,
AI_BASE2 and AI_SIZE are always ’0’).
The DSPCPU is required to assign a new, empty buffer
to BASE1 and perform an ACK1, before buffer 2 fills up.
Capture continues in buffer 2, until it fills up. At that time,
BUF2_FULL is asserted, and capture continues in the
new buffer 1, etc.
Upon receipt of an ACK, the AI hardware removes the re-
lated interrupt request line assertion at the next DSPCPU
clock edge. Refer to
(Maskable and Non-Maskable Interrupts),”
regarding ACK and interrupt re-enabling. The AI interrupt
should always be operated in level-sensitive mode, since
AI can signal multiple conditions that each need indepen-
dent ACKs over the single internal SOURCE 11 request
line.
In normal operation, the DSPCPU and AI hardware con-
tinuously exchange buffers without ever loosing a sam-
ple. If the DSPCPU fails to provide a new buffer in time,
the OVERRUN error flag is raised. This flag is not affect-
ed by ACK1 or ACK2; it can only be cleared by an explicit
ACK_OVR.
8.8
The AI unit enters power down state whenever PNX1300
is put in global power down mode, except if the SLEEP-
LESS bit in AI_CTL is set. In the latter case, the unit con-
tinues DMA operation and will wake up the DSPCPU
whenever an interrupt is generated.
The AI unit can be separately powered down by setting a
bit in the BLOCK_POWER_DOWN register. Refer to
Chapter 21, “Power Management.”
It is recommended that AI be stopped (by negating
AI_CTL.CAP_ENABLE) before block level power down
is started, or that SLEEPLESS mode is used when global
power down is activated.
8.9
The AI unit uses internal buffering before writing data to
SDRAM. The internal buffer consists of one stereo sam-
ple input holding register and 64 bytes of internal buffer
memory. Under normal operation, the 64-byte buffer is
written to SDRAM while the input register receives an-
other sample. This normal operation is guaranteed to be
maintained as long as the highway arbiter is set to guar-
antee a latency for the AI unit that matches the sampling
interval. Given a sample rate f
ple interval T (in nsec), the arbiter should be set to have
a latency of at most T-20 nsec. Refer to
biter,”
quested latency is not adequate, the HBE (Highway
Bandwidth Error) condition may result. This error flag
gets set when the input register is full, the 64-byte buffer
for information on arbiter programming. If the re-
POWER DOWN AND SLEEPLESS
HIGHWAY LATENCY AND HBE
Section 3.5.3, “INT and NMI
s
, and an associated sam-
Chapter 20, “Ar-
for the rules
has not yet been written to memory, and a new sample
arrives.
Table 8-10
a number of common operating modes. The rightmost
column illustrates the nature of the resulting 64-byte
highway requests. Is not necessary to compute arbiter
settings, but they may be used to compute bus availabil-
ity in a given interval.
Table 8-10. AI highway arbiter latency requirement
examples
8.10
If either an OVERRUN or HBE error occurs, input sam-
pling is temporarily halted, and samples will be lost. In
case of OVERRUN, sampling resumes as soon as the
DSPCPU makes one or more new buffers available
through an ACK1 or ACK2 operation. In the case of HBE,
sampling will resume as soon as the internal buffer is
written to SDRAM.
HBE and OVERRUN are ‘sticky’ error flags. They will re-
main set until an explicit ACK_HBE or ACK_OVR.
8.11
Diagnostic mode is entered by setting the DIAGMODE
bit in the AI_CTL register. In diagnostic mode, the
AI_SCK, AI_WS and AI_SD inputs of the serial-parallel
converter are taken from the output pins of the PNX1300
AO unit. This mode can be used during the diagnostic
phase of system boot to verify correct operation of most
of the AI unit and AO unit logic circuitry.
Note that the inputs are truly taken from the PNX1300
AO external pins, i.e. if an external (board level) source
is driving AO_SCK or AO_WS, diagnostic mode is not
capable of testing Audio Out.
Special care must be taken to enable diagnostic mode.
The recommended way of entering diagnostic mode is:
• setup the AO unit such that an AO_SCK is generated
• set DIAGMODE bit followed by a 5 (AI_SCK) cycle
• perform a software reset of the AI unit and immedi-
PRELIMINARY SPECIFICATION
stereo
16 bits/sample
stereo
16 bits/sample
stereo
16 bits/sample
CapMode
delay
ately set the DIAGMODE bit back to ‘1’.
ERROR BEHAVIOR
DIAGNOSTIC MODE
shows the required arbiter latency settings for
(kHz)
44.1
48.0
96.0
f
s
22,676
20,833
10,417
(nS)
T
latency
arbiter
22,656
20,813
10,397
(nsec)
max
access pattern
1 request every
1 request every
1 request every
362,812 nsec
333,333 nsec
166,667 nsec
Audio In
8-7