PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 67

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
device events lead to the request of an interrupt. In addi-
tion, the PCSW.IEN flag determines whether the
DSPCPU is willing to handle regular interrupts. Non
maskable interrupts ignore the state of this flag.
All three mechanisms are necessary: the PCSW.IEN flag
is used to implement critical sections of code during
which the RTOS (real-time operating system) is unable
to handle regular interrupts. The IMASK is used to allow
full control over interrupt handler nesting. The device in-
terrupt flags set the operational mode of the device.
When RESET is asserted, IPENDING, ICLEAR, and
IMASK are set to all zeroes. (MMIO register addresses
shown in
MMIO_BASE.)
3.5.3.6
The IPENDING register shown in
to observe the currently pending interrupts. Each bit read
depends on the mode of the source:
• For a level-sensitive source, a bit value corresponds
• For an edge-triggered interrupt, a ‘1’ is read if and
Software can request an interrupt for sources operating
in edge-triggered mode. Writes to the IPENDING register
assert an interrupt request for all sources where a 1 oc-
curred in the bit position of the written value. The state of
sources where a 0 occurred in the written value is un-
changed. Writes have no effect on level-sensitive mode
sources. The interrupt request, if not masked, will occur
at the next successful interruptible jump. This differs from
the conventional software interrupt-like semantics of
many architectures. Any of the 32 sources can be re-
quested in software. In normal operation however, soft-
ware-requested interrupts should be limited to source
vectors not allocated for hardware devices. Note that an-
other PCI master can request interrupts by manipulating
the IPENDING location in the MMIO aperture. This is
useful for inter-processor communication.
Figure 3-8. Interrupt controller request, clear, and mask MMIO registers.
to the current state of the device interrupt request
line.
only if an interrupt request occurred and the corre-
sponding vector has not yet been dispatched.
MMIO_BASE
0x10 0828
0x10 0824
0x10 0820
offset:
Figure 3-8
Software interrupts and
acknowledgment
are offset addresses with respect to
IMASK (r/w)
ICLEAR (r/w)
IPENDING (r/w)
Figure 3-8
31
Each IPENDING(i) bit:
Each IMASK(i) bit:
Each ICLEAR(i) bit:
can be read
On read or write, 0 ⇒ disallow source i interrupt request
On read, 1 ⇒ source i interrupt request is pending
On write, 1 ⇒ software source i interrupt request
On read or write, 1 ⇒ allow source i interrupt request
On read, same as IPENDING(i)
On write, 1 ⇒ clear source i interrupt request
23
The ICLEAR register reads the same as the IPENDING
register. Writes to the ICLEAR register serve to clear
pending flags for edge-triggered mode sources. All IP-
ENDING flags corresponding to bit positions in which ‘1’s
are written are cleared. IPENDING flags corresponding
to bit positions in which ‘0’s are written are not affected.
Writes have no effect on level-sensitive mode sources.
When a pending interrupt bit is being cleared through a
write to the ICLEAR register at the same time that the
hardware is trying to set that interrupt bit, the hardware
takes precedence.
3.5.3.7
In most applications, it is desirable not to nest NMIs. The
NMI interrupt handler can accomplish this by saving the
old IMASK content and clearing IMASK before the first
interruptible jump is executed by the NMI handler.
3.5.3.8
Table 3-10
source numbers, as well as the recommended operating
mode (edge or level triggered). Note that there are a total
of 5 external pins available to assert interrupt requests.
The PCI INTA to INTD requests are asserted by active
low signal conventions, i.e. a zero level or a negative
edge asserts a request. The USERIRQ pin operates with
active high signalling conventions.
3.6
In systems where PNX1300 is operating in the presence
of a host CPU on PCI, PNX1300 can generate interrupts
to the host, using any combination of the four PCI INTA#
to INTD# pins. In a typical host system, only one of these
pins needs to be wired to the PCI bus interrupt request
lines. Any unused pins of this group are then available for
use as software programmable I/O pins.
The INT_CTL register (see
set, enable the open collector driver of the four
INTD#..INTA# pins. The INTx bits determine the output
value generated (if enabled). A ‘1’ in INTx causes the
corresponding PCI interrupt pin to be asserted (low IN-
Tx# pin). The ISx bits are read-only and reflect the cur-
PRELIMINARY SPECIFICATION
PNX1300 TO HOST INTERRUPTS
shows the assignment of devices to interrupt
NMI sequentialization
Interrupt source assignment
15
Figure
DSPCPU Architecture
7
3-9) IEx bits, when
3-11
0