PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 69

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Figure 3-10. Timer register definitions.
Table 3-11. Timer base MMIO address
Table 3-12. Timer source selections
the counter will have to loop around before an interrupt is
generated.
A modulus value of zero causes a wrap-around as if the
modulus value was 2
On RESET, the TCTL registers are cleared, and the val-
ue of the TMODULUS and TVALUE registers is unde-
fined.
TIMER1
TIMER2
TIMER3
SYSTIMER
CLOCK
PRESCALE
TRI_TIMER_CLK
DATABREAK
INSTBREAK
CACHE1
CACHE2
VI_CLK
VO_CLK
AI_WS
AO_WS
SSI_RXFSX
SSI_IO2
—
Timer base offset:
Source Name
0
4
8
TMODULUS (r/w)
TVALUE (r/w)
TCTL (r/w)
MMIO_BASE+0x10,0C60
MMIO_BASE+0x10,0C00
MMIO_BASE+0x10,0C20
MMIO_BASE+0x10,0C40
Source
Value
13-15
Bits
32
10
12
11
0
1
2
3
4
5
6
7
8
9
.
CPU clock
prescaled CPU clock
external clock pin
data breakpoints
instruction breakpoints
cache event 1
cache event 2
video in clock pin
video out clock pin
audio in word strobe pin
audio out word strobe pin
SSI receive frame sync pin
SSI transmit frame sync pin
undefined
Source Description
31
“PRESCALE”:
Prescale value is
2^PRESCALE, i.e.,
in the range [1..32768]
27
23
3.9
This section describes the special debug support offered
by the DSPCPU. Instruction and data breakpoints can be
defined through a set of registers in the MMIO register
space. When a breakpoint is matched, an event is gen-
erated that can be used as a timer source (see
3.8,
generate a DSPCPU interrupt after the desired number
of breakpoint matches.
3.9.1
The instruction-breakpoint control register is shown in
Figure
(MMIO-register addresses shown are offset with respect
to MMIO_BASE.)
The instruction-breakpoint address-range registers are
shown in
registers is undefined. (MMIO-register addresses shown
are offset with respect to MMIO_BASE.)
When the IC bit in the breakpoint control register is set to
‘1’, instruction breakpoints are activated. Any instruction
address issued by the PNX1300 chip is compared
against the low and high address-range values. The IAC
bit in the breakpoint control register determines whether
the instruction address needs to be inside or outside of
the range defined by the low and high address-range
registers. A successful comparison takes place when ei-
ther:
•
•
On a successful comparison, an instruction breakpoint
event is generated, which can be used as a clock input
to a timer. After counting the programmed number of in-
struction breakpoint events, the timer will generate an in-
terrupt request.
PRELIMINARY SPECIFICATION
IAC = ‘0’ and low ≤ iaddr ≤ high, or
IAC = ‘1’ and iaddr < low or iaddr > high.
“Timers”). The timer TMODULUS has to be set to
19
PRESCALE
3-11. On RESET, the BICTL register is cleared.
DEBUG SUPPORT
MODULUS
“SOURCE” select:
see table
Figure
Instruction Breakpoints
VALUE
15
3-12. After RESET, the value of these
Table 3-12
11
SOURCE
DSPCPU Architecture
7
“RUN” bit:
0
1
Timer stopped
Timer running
3
Section
R
0
3-13