PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 433

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
lsr
SYNTAX
FUNCTION
DESCRIPTION
amount, and rsrc1 is logically shifted right by this amount. If the rsrc2<31:5> value is not zero, then take this as a shift
by 32 or more bits. Zeros fill vacated bits from the left.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
A-135
r30 = 0x7008000f, r20 = 1
r30 = 0x7008000f, r42 = 2
r10 = 0, r30 = 0x7008000f, r44 = 4
r20 = 1, r30 = 0x7008000f, r44 = 4
r40 = 0x80030007, r44 = 4
r30 = 0x7008000f, r45 = 0x1f
r30 = 0x8008000f, r45 = 0x1f
r30 = 0x7008000f, r45 = 0x20
r30 = 0x8008000f, r45 = 0x80000000
r30 = 0x8008000f, r45 = 0x23
As shown below, the
The
[ IF rguard ] lsr rsrc1 rsrc2 → rdest
if rguard then {
}
rsrc1
n ← rsrc2<4:0>
rdest<31:32–n> ← 0
rdest<31–n:0> ← rsrc1<31:n>
if rsrc2<31:5> != 0 {
}
rdest <- 0
lsr
S
31
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
Intermediate result
PRELIMINARY SPECIFICATION
(example: n = 3)
lsr
operation takes two arguments, rsrc1 and rsrc2. Rsrc2 specifies an unsigned shift
rdest
lsr r30 r20 → r50
lsr r30 r42 → r60
IF r10 lsr r30 r44 → r70
IF r20 lsr r30 r44 → r80
lsr r40 r44 → r90
lsr r30 r45 → r100
lsr r30 r45 → r100
lsr r30 r45 → r100
lsr r30 r45 → r100
lsr r30 r45 → r100
31
0
0
0
0
0
0
28
S
S
0
Operation
Right shifter
32 bits from rsrc1
rsrc2
31
r50 ← 0x38040007
r60 ← 0x1c020003
no change, since guard is false
r80 ← 0x07008000
r90 ← 0x08003000
r100 ← 0x00000000
r100 ← 0x00000001
r100 ← 0x00000000
r100 ← 0x00000000
r100 ← 0x00000000
0
asl asli asr asri lsl lsli
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
Philips Semiconductors
Logical shift right
lsri rol roli
ATTRIBUTES
SEE ALSO
rsrc2
Result
shifter
1, 2
No
96
—
0
2
1