PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 336

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Floating-point absolute value
SYNTAX
FUNCTION
DESCRIPTION
values are in IEEE single-precision floating-point format. If an argument is denormalized, zero is substituted for the
argument before computing the absolute value, and the IFZ flag in the PCSW is set. If
exception, the corresponding exception flags in the PCSW are set. The PCSW exception flags are sticky: the flags
can be set as a side-effect of any floating-point operation but can only be reset by an explicit
The update of the PCSW exception flags occurs at the same time as rdest is written. If any other floating-point
compute operations update the PCSW at the same time, the net result in each exception flag is the logical OR of all
simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0)
r35 = 0xbf800000 (-1.0)
r40 = 0x00400000 (5.877471754e-39)
r45 = 0xffffffff (QNaN)
r50 = 0xffbfffff (SNaN)
r10 = 0,
r55 = 0xff7fffff (–3.402823466e+38)
r20 = 1,
r55 = 0xff7fffff (–3.402823466e+38)
The
The
The
[ IF rguard ] fabsval rsrc1 → rdest
if rguard then {
}
if (float)rsrc1 < 0 then
else
fabsvalflags
fabsval
fabsval
rdest ← –(float)rsrc1
rdest ← (float)rsrc1
Initial Values
operation computes the absolute value of the argument rsrc1 and stores the result into rdest. All
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the exception flags that would result from an individual
fabsval r30 → r90
fabsval r35 → r95
fabsval r40 → r100
fabsval r45 → r105
fabsval r50 → r110
IF r10 fabsval r55 → r115
IF r20 fabsval r55 → r120
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r90 ← 0x40400000 (3.0)
r95 ← 0x3f800000 (1.0)
r100 ← 0x0 (+0.0), IFZ set
r105 ← 0xffffffff (QNaN)
r110 ← 0xffffffff (QNaN), INV set
no change, since guard is false
r120 ← 0x7f7fffff (3.402823466e+38)
iabs dspiabs dspidualabs
fabsvalflags readpcsw
fabsval
ATTRIBUTES
writepcsw
writepcsw
SEE ALSO
Result
causes an IEEE
fabsval
fabsval
operation.
falu
115
1, 4
No
—
1
3
.
A-38