PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 31

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
VI_CLK
VI_DVALID
VI_DATA0
VI_DATA1
VI_DATA2
VI_DATA3
VI_DATA4
VI_DATA5
VI_DATA6
VI_DATA7
VI_DATA8
VI_DATA9
IIC_SDA
IIC_SCL
VO_DATA0
VO_DATA1
VO_DATA2
VO_DATA3
VO_DATA4
VO_DATA5
VO_DATA6
VO_DATA7
Pin Name
BGA
M18
M19
M20
Ball
F20
F18
F19
E20
C20
A17
D18
C19
B20
B19
A20
A19
C17
B18
A18
B17
R19
R20
P20
N19
N20
K19
J20
C9
A8
B8
A7
WEAK5
WEAK5
WEAK5
WEAK5
WEAK5
WEAK5
WEAK5
WEAK5
STRG5
PCIOD
PCIOD
PCIOD
IICOD
IICOD
Type
Pad
PCI
JTAG Interface (debug access port and 1149.1 boundary scan port)
I/O/OD
Mode
I/OD
I/OD
I/OD
I/OD
I/OD
OUT
I/O
I/O
IN
IN
IN
IN
IN
IN
• Can operate as input (power up default) or output, as determined by direction con-
• As input, a PCI_INT# pin can be used to receive PCI interrupt requests (normal PCI
• As output, the value of a PCI_INT# can be programmed through PCI MMIO regis-
• Whenever XIO bus functionality is active, PCI_INTB# is a push-pull CMOS I/O pin.
JTAG test data input
JTAG test data output. This pin can either drive active low, high or float.
JTAG test clock input
JTAG test mode select input
• If configured as input (power up default): a positive transition on this incoming video
• If configured as output: programmable output clock to drive an external video A/D
If used as output, a board level 27-33 ohm series resistor is recommended to reduce
ringing.
VI_DVALID indicates that valid data is present on the VI_DATA lines. If HIGH,
VI_DATA will be accepted on the next VI_CLK positive edge. If LOW, no VI_DATA will
be sampled. PNX1300 Series supports an additional mode where VI_DATA[9:8] in
message passing mode are not affected by the VI_DVALID signal,
page
CCIR656 style YUV 4:2:2 data from a digital camera, or general purpose high speed
data input pins. Sampled on VI_CLK if VI_DVALID HIGH.
Extension high speed data input bits to allow use of 10 bit video A/D converters in
raw10 modes. VI_DATA[8] serves as START and VI_DATA[9] as END message input
in message passing mode. Sampled on positive transitions of VI_CLK if VI_DVALID
HIGH. PNX1300 Series supports an additional mode where VI_DATA[9:8] in message
passing mode are not affected by the VI_DVALID signal,
I
I
CCIR656 style YUV 4:2:2 digital output data, or general purpose high speed data out-
put channel. Output changes on positive edge of VO_CLK.
2
2
C serial data
C clock
trol bits in PCI MMIO register INT_CTL.
use is active low, level sensitive mode, but the VIC can be set to treat these as pos-
itive edge triggered mode). As input, a PCI_INT# pin can also be used as a general
interrupt request pin if not needed for PCI.
ters to generate interrupts for other PCI masters.
When the XIO bus is not active and regular PCI bus functionality is activated, then
PCI_INTB# has a PCI compatible open drain output.
clock pin samples all other VI_DATA input signals below if VI_DVALID is HIGH. If
VI_DVALID is LOW, VI_DATA is ignored. Clock and data rates of up to 81 MHz are
supported. PNX1300 Series supports an additional mode where VI_DATA[9:8] in
message passing mode are not affected by the VI_DVALID signal,
page
converter. Can be programmed to emit integral dividers of DSPCPU_CLK.
6-12.
6-12.
I
2
Video Out
C Interface
Video In
PRELIMINARY SPECIFICATION
Description
Section 6.6.1 on page
Section 6.6.1 on
Section 6.6.1 on
Pin List
6-12.
1-5