MA180023 Microchip Technology, MA180023 Datasheet - Page 50

MODULE PLUG-IN PIC18F46J11 PIM

MA180023

Manufacturer Part Number
MA180023
Description
MODULE PLUG-IN PIC18F46J11 PIM
Manufacturer
Microchip Technology
Series
PIC®r
Datasheet

Specifications of MA180023

Accessory Type
Plug-In Module (PIM) - PIC18F46J11
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
PIC18
Supported Devices
Stand-alone Or W/ HPC(DM183022) Or PIC18(DM183032)
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC18
Silicon Core Number
PIC18F
Silicon Family Name
PIC18FxxJxx
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
HPC Explorer Board (DM183022) or PIC18 Explorer Board (DM183032)
For Use With
DM183032 - BOARD EXPLORER PICDEM PIC18DM183022 - BOARD DEMO PIC18FXX22 64/80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MA180023
Manufacturer:
Microchip Technology
Quantity:
135
Deep Sleep wake-up events are only monitored while
PIC18F46J11 FAMILY
3.6.3
While in Deep Sleep mode, the device can be awakened
by a MCLR, POR, RTCC, INT0 I/O pin interrupt,
DSWDT or ULPWU event. After waking, the device per-
forms a POR. When the device is released from Reset,
code execution will begin at the device’s Reset vector.
The software can determine if the wake-up was caused
from an exit from Deep Sleep mode by reading the DS
bit (WDTCON<3>). If this bit is set, the POR was
caused by a Deep Sleep exit. The DS bit must be
manually cleared by the software.
The software can determine the wake event source by
reading the DSWAKEH and DSWAKEL registers.
When the application firmware is done using the
DSWAKEH and DSWAKEL status registers, individual
bits do not need to be manually cleared before entering
Deep Sleep again. When entering Deep Sleep mode,
these registers are automatically cleared.
3.6.3.1
the processor is fully in Deep Sleep mode. If a wake-up
event occurs before Deep Sleep mode is entered, the
event status will not be reflected in the DSWAKE regis-
ters. If the wake-up source asserts prior to entering
Deep Sleep, the CPU may go to the interrupt vector (if
the wake source has an interrupt bit and the interrupt is
fully enabled), and may abort the Deep Sleep entry
sequence by executing past the SLEEP instruction. In
this case, a wake-up event handler should be placed
after the SLEEP instruction to process the event and
re-attempt entry into Deep Sleep if desired.
When the device is in Deep Sleep with more than one
wake-up source simultaneously enabled, only the first
wake-up source to assert will be detected and logged
in the DSWAKEH/DSWAKEL status registers.
DS39932C-page 50
DEEP SLEEP WAKE-UP SOURCES
Wake-up Event Considerations
DSWDTOSC bit (CONFIG3L<0>).
optionally enabled through the DSBOREN Configuration
3.6.4
Deep Sleep has its own dedicated WDT (DSWDT) with
a postscaler for time-outs of 2.1 ms to 25.7 days,
configurable
(CONFIG3L<7:4>).
The DSWDT can be clocked from either the INTRC or
the T1OSC/T1CKI input. If the T1OSC/T1CKI source will
be used with a crystal, the T1OSCEN bit in the T1CON
register needs to be set prior to entering Deep Sleep.
The reference clock source is configured through the
DSWDT is enabled through the DSWDTEN bit
(CONFIG3L<3>). Entering Deep Sleep mode automati-
cally clears the DSWDT. See Section 25.0 “Special
Features of the CPU” for more information.
3.6.5
The Deep Sleep module contains a dedicated Deep
Sleep BOR (DSBOR) circuit. This circuit may be
bit (CONFIG3L<2>).
The DSBOR circuit monitors the V
voltage. The behavior of the DSBOR circuit is
described in Section 4.4 “Brown-out Reset (BOR)”.
3.6.6
The RTCC can operate uninterrupted during Deep
Sleep mode. It can wake the device from Deep Sleep by
configuring an alarm.
The RTCC clock source is configured with the RTCOSC
bit (CONFIG3L<1>). The available reference clock
sources are the INTRC and T1OSC/T1CKI. If the INTRC
is used, the RTCC accuracy will directly depend on the
INTRC tolerance. For more information on configuring
the RTCC peripheral, see Section 16.0 “Real-Time
Clock and Calendar (RTCC)”.
DEEP SLEEP WATCHDOG TIMER
(DSWDT)
DEEP SLEEP BROWN OUT RESET
(DSBOR)
RTCC PERIPHERAL AND DEEP
SLEEP
through
© 2009 Microchip Technology Inc.
the
bits,
DSWDTPS<3:0>
DD
supply rail

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