MA180023 Microchip Technology, MA180023 Datasheet - Page 140

• Manufacturer Part Number: MA180023
• Description: MODULE PLUG-IN PIC18F46J11 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180023

• Accessory Type: Plug-In Module (PIM) - PIC18F46J11
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: PIC18
• Supported Devices: Stand-alone Or W/ HPC(DM183022) Or PIC18(DM183032)
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: HPC Explorer Board (DM183022) or PIC18 Explorer Board (DM183032)
• For Use With: DM183032 - BOARD EXPLORER PICDEM PIC18DM183022 - BOARD DEMO PIC18FXX22 64/80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
TABLE 9-9:
DS39932C-page 140
RD0/PMD0/
SCL2
RD1/PMD1/
SDA2
RD2/PMD2/
RP19
RD3/PMD3/
RP20
RD4/PMD4/
RP21
RD5/PMD5/
RP22
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
Pin
input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PORTD I/O SUMMARY
Function
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
SDA2
SCL2
RP19
RP20
RP21
RP22
RD0
RD1
RD2
RD3
RD4
RD5
Setting
TRIS
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
II
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
Type
SMB
SMB
DIG
DIG
I
DIG
DIG
TTL
DIG
I
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
2
2
C/
C/
PORTD<0> data input.
LATD<0> data output.
Parallel Master Port data out.
I
module setting.
I
data.
PORTD<1> data input.
LATD<1> data output.
Parallel Master Port data in.
Parallel Master Port data out.
I
module setting.
I
data.
PORTD<2> data input.
LATD<2> data output.
Parallel Master Port data in.
Parallel Master Port data out.
Remappable peripheral pin 19 input.
Remappable peripheral pin 19 output.
PORTD<3> data input.
LATD<3> data output.
Parallel Master Port data out.
Remappable peripheral pin 20 input.
Remappable peripheral pin 20 output.
PORTD<4> data input.
LATD<4> data output.
Parallel Master Port data in.
Parallel Master Port data out.
Remappable peripheral pin 21 input.
Remappable peripheral pin 21 output.
PORTD<5> data input.
LATD<5> data output.
Parallel Master Port data in.
Parallel Master Port data out.
Remappable peripheral pin 22 input.
Remappable peripheral pin 22 output.
2
2
2
2
C™ clock input (MSSP2 module); input type depends on
C™ clock output (MSSP2 module); takes priority over port
C data input (MSSP2 module); input type depends on
C data output (MSSP2 module); takes priority over port
Description
© 2009 Microchip Technology Inc.
2
C/SMB = I
2
C/SMBus