MA180023 Microchip Technology, MA180023 Datasheet - Page 44

• Manufacturer Part Number: MA180023
• Description: MODULE PLUG-IN PIC18F46J11 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180023

• Accessory Type: Plug-In Module (PIM) - PIC18F46J11
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: PIC18
• Supported Devices: Stand-alone Or W/ HPC(DM183022) Or PIC18(DM183032)
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: HPC Explorer Board (DM183022) or PIC18 Explorer Board (DM183032)
• For Use With: DM183032 - BOARD EXPLORER PICDEM PIC18DM183022 - BOARD DEMO PIC18FXX22 64/80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications, which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting the SCS<1:0> bits
(OSCCON<1:0>) to ‘11’. When the clock source is
switched
Figure 3-3), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 3-3:
FIGURE 3-4:
DS39932C-page 44
Peripheral
Program
Counter
INTRC
OSC1
to
Note 1: T
Clock
Clock
RC_RUN MODE
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
INTRC
Output
the
OSC1
Clock
Q1
SCS<1:0> Bits Changed
internal
OST
Q2
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
PC
Q3
= 1024 T
Q4
oscillator
Q1
OSC
Q1
T
; T
1
OST
PLL
(1)
PC
block
Q2
2
= 2 ms (approx). These intervals are not shown to scale.
Clock Transition
3
T
OSTS Bit Set
PLL
(see
Q3
(1)
PC + 2
Q4
n-1
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
block while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the OSTS bit is set and the primary
clock is providing the device clock. The IDLEN and
SCS bits are not affected by the switch. The INTRC
clock source will continue to run if either the WDT or the
FSCM is enabled.
n
Q1
1
Transition
2
Clock
n-1 n
Q2
PC + 2
Q3
Q2
Q4
© 2009 Microchip Technology Inc.
Q3 Q4
Q1
Q1
PC + 4
Q2
Q2
PC + 4
Q3
Q3