MA180023 Microchip Technology, MA180023 Datasheet - Page 288

• Manufacturer Part Number: MA180023
• Description: MODULE PLUG-IN PIC18F46J11 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180023

• Accessory Type: Plug-In Module (PIM) - PIC18F46J11
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: PIC18
• Supported Devices: Stand-alone Or W/ HPC(DM183022) Or PIC18(DM183032)
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: HPC Explorer Board (DM183022) or PIC18 Explorer Board (DM183032)
• For Use With: DM183032 - BOARD EXPLORER PICDEM PIC18DM183022 - BOARD DEMO PIC18FXX22 64/80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
REGISTER 18-7:
DS39932C-page 288
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GCEN
R/W-0
2:
3:
(3)
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I
(or writes to the SSPxBUF are disabled).
This bit is not implemented in I
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit
1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Stop condition Idle
RSEN: Repeated Start Condition Enable bit
1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Repeated Start condition Idle
SEN: Start Condition Enable bit
1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Start condition Idle
ACKSTAT
2
R/W-0
C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
automatically cleared by hardware
SSPxCON2: MSSPx CONTROL REGISTER 2 –I
(ACCESS FC5h/F71h)
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
(1)
2
C Master mode.
ACKEN
(2)
(2)
2
C
R/W-0
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
RCEN
R/W-0
(3)
(2)
(2)
(1)
PEN
2
R/W-0
C™ MASTER MODE
(2)
© 2009 Microchip Technology Inc.
x = Bit is unknown
RSEN
R/W-0
(2)
SEN
R/W-0
(2)
bit 0