cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 96

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
Table 5-4. Service Request Pointer Register
5.2.1.1
5-6
31:3
2:0
Bit
SRQ_PTR[31:3]
SRQ_PTR[2:0]
Field Name
The Service Request Pointer register provides the address of the Service Request
Descriptor Table (see
shared memory.
Service Request Descriptors
A Service Request Descriptor (SRD) is a 4-dword location in shared memory.
Actually, one represents an entry in the SRD table. The SRD is defined as a union
type in C, which allows different commands to be configured in a 4-dword space. The
SRD can handle three different configurations: Device Configuration Descriptor
(DCD), EBUS Configuration Descriptor (ECD), and Channel Configuration
Descriptor (CCD).
A list of service request commands is defined as a sequence of SRDs. The following
instructions, referred to in the document as OPCODE, are supported:
Table 5-5
A service request is issued to a specific channel, or per whole device. On completion
of each service request command, an acknowledgment interrupt is generated (Service
Acknowledge - SACK) and sent to the host. This interrupt may be disabled per
service request by setting the SACKIEN bit of the SRD to 0. It is possible for the host
to issue multiple service requests successively without expecting or receiving
acknowledgments from each request if the SACKIEN bit was not set accordingly in
the SRD.
One mode of operation is for the host to set the SACKIEN bit in only the last SRD so
if a SACK Service Request Acknowledge interrupt is received, it will validate the
whole list of service request commands.
Activate and Deactivate commands could take a long time before they are actually
executed by the CX28560. The CX28560 returns the SACK (if SACKIEN bit is set)
immediately after it started the command execution. Therefore, the host may not
assume the command was actually executed just by detecting the SACK was returned.
Another interrupt, End Of Command Execution (EOCE), is defined for each of these
commands. The host may assume the command was actually executed only after
receiving the appropriate EOCE.
Value
—
• Configure a port/channel
• Read the CX28560 register or counters
• Expansion Bus (EBUS) read command
• EBUS write command
• Activate a channel
• Deactivate a channel
• No-operation command
0
defines the Service Request Descriptor OPCODE.
Service Request Pointer. These 29 bits are appended with 000b to form a 32-bit address
Quadword aligned. This address points to the first entry on the Service Request
Descriptor Table allocated in shared memory.
To ensure Quadword alignment.
Mindspeed Technologies™
Advance Information
Table
5-4). Host needs to allocate and initialize this table in
Description
CX28560 Data Sheet
28560-DSH-001-B