cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 194

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Electrical and Mechanical Specification
Figure 8-14. Transmit and Receive T1 Mode
8-18
NOTE(S):
1. T1 Mode employs 24 time slots (0–23) with 8 bits per time slot (0–7) and 1 Frame-bit every 193 clock periods. One frame
2. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period.
3. CX28560 can be configured to sample RSYNC, TSYNC, RDAT, and TDAT on either a rising or falling clock edge
4. Relationships between the various configurations of active edges for the synchronization signal and the data signal are
5. All received signals (e.g., RSYNC, RDAT, TSYNC) are “sampled” in on the specified clock edge (e.g., RCLK, TCLK). All
6. In configuration (a), synchronization and data signals are sampled/latched on a rising clock edge.
7. In configuration (b), synchronization signal is sampled on a rising clock edge and the data signal is sampled/latched on a
8. In configuration (c), synchronization signal is sampled on a falling clock edge and the data signal is sampled/latched on a
9. In configuration (d), synchronization and data signals are sampled/latched on a falling clock edge.
of 193 bits occurs every 125 µs (1.544 MHz).
independently of any other signal sampling configuration.
shown using a common clock signal for receive and transmit operations. Note the relationship between the frame bit
(within RDAT, TDAT) and the frame synchronization signal (e.g., RSYNC, TSYNC).
transmit data signals (TDAT) are latched on the specified clock edge.
falling clock edge.
rising clock edge.
RSYNC-RISE(a)
RSYNC-RISE(b)
RSYNC-FALL(c)
RSYNC-FALL(d)
TSYNC-RISE(a)
TSYNC-RISE(b)
TSYNC-FALL(c)
TSYNC-FALL(d)
RDATA-RISE(a)
RDATA-RISE(c)
TDATA-FALL(b)
TDATA-FALL(d)
RDAT-FALL(b)
RDAT-FALL(d)
TDAT-RISE(a)
TDAT-RISE(c)
RCLK
TCLK
Mindspeed Technologies™
Advance Information
CX28560 Data Sheet
28560-DSH-001-B