cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 50

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Host Interfaces
2.1.1.3
2-4
Fast Back-to-Back Transactions
Fast back-to-back transactions allow agents to use bus bandwidth more effectively.
the CX28560 supports PCI fast back-to-back transactions both as a bus target and bus
master. the CX28560 can also execute fast back-to-back transactions regardless of the
PCI configuration settings (for details see bit 11 TARGET_FBTB bit field in
5.0).
NOTE:
Fast back-to-back transactions are allowed on PCI when contention on TRDY*,
DEVSEL*, STOP*, or PERR* is avoided. (for a detailed description of these pins see
Chapter
The CX28560, as a master supporting fast back-to-back transactions, places the
burden of avoiding contention on itself. While acting as a slave, the CX28560 places
the burden on all the potential targets. As a master, the CX28560 may remove the Idle
state between transactions when it can guarantee that no contention occurs. This can
be accomplished when the master’s current transaction is to the same target as the
previous transaction. While supporting this type of fast back-to-back transaction, the
CX28560 understands the address boundaries of the potential target, so that no
contention occurs. The target must be able to detect a new assertion of FRAME*
without the bus going to idle state.
Operation Mode
During a fast back-to-back transaction, the master starts the next transaction if GNT*
is still asserted. If GNT* is deasserted, the master has lost access to the bus and must
relinquish the bus to the next master. The last data phase completes when FRAME* is
deasserted, and IRDY* and TRDY* (or STOP*) are asserted. The current master
starts another transaction on the clock following the completion of the last data phase
of the previous transaction. During fast back-to-back transaction, only the master and
target involved need to distinguish intermediate transaction boundaries using only
FRAME* and IRDY* (there is no bus Idle state). When the transaction is over, all the
agents see an Idle state.
Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-Back
Transactions
Appendix G shows an example of an arbitration for fast back-to-back and non-fast
back-to-back transactions. The transactions shown are bursts of 2 or 3 dwords.
The CX28560 will only perform Fast Back to Back between transactions from
different sources (either the Interrupt Controller or the Host Service Unit) and
not between transactions from the same source.
1.0).
Mindspeed Technologies™
Advance Information
CX28560 Data Sheet
28560-DSH-001-B
Chapter