cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 215

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
A.4
A.4.1
Table A-1. Service Request Routine Field for Counter Read (Receive)
28560-DSH-001-B
OPCODE
SACKIEN
LENGTH
Shared Memory Pointer
CX28560 BASE
Descriptor Field
Reading Counters
Receive Direction
5
1
14
30 + 2
22 + 2
The reading of the values of latched counters is performed via service routine requests
over the PCI.
In the receive direction, the channels are arranged in the CX28560’s memory in
groups of 8 register addresses (7 counters + 1 reserved). To read all counters for
channel N, create a service request routine with the fields listed in
Size
Mindspeed Technologies™
CONFIG_RD
0—SACK interrupt disabled.
1—SACK interrupt enabled.
An appropriate interrupt is generated after the command is completed.
Number of double words in the memory transaction request.
If 0, the number of transfers is 16 K. Therefore it allows for any number of
dwords of 1–16384.
To read all the receive counters for one channel, this should be set to 8.
To read all the counters of all the channels, this should be set to 16384.
The pointer is dword-aligned by concatenating two zeros to the lsb and making
it a 32-bit pointer. This address is set according to the system’s needs.
The CX28560 base (dword-aligned) address for a memory transaction request.
The CX28560 base addresses are specified in bytes but dword-aligned, i.e., with
the 2 LSbs as 00.
To read channel N’s counters, this should be set to (suffixed by 00 for dword
alignment):
(COUNTER BASE ADDRESS = 22’h008000) + (8 * N)
To read all the channels’ counters, this should be set to (suffixed by 00 for
dword alignment):
(COUNTER BASE ADDRESS = 22’h008000)
Shared memory base address for a memory transaction request.
Advance Information
Description
Table
A-1.
Counters
A
-
5