cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 84

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Serial Interface
4.6.5
4.6.6
4-10
Channel Clear To Send (CTS)
Frame Alignment
The CX28560’s transmit path can be configured to obey a Channel Clear To Send
(CTS) external signal on a per-port basis by enabling the CTS_ENB bit in the
TSIU Port Configuration register. CTS is sampled on the specified active edge of
TCLK depending on CTS_EDGE.
If CTS is deasserted (low), the channel assigned to the time slot sends continuous
idle characters after the current message has been completely transmitted. If CTS
is asserted (high), message transmission continues. When configured to operate
in CTS mode, the channels of this specific port will not start a new message
transmission if the CTS is a logical 0. The channel response time to react to
changes in the channel CTS signal is 32 bits.
To maintain a time-base, in conventional mode, the CX28560 uses the TSYNC
and RSYNC signals. These signals keep track of the active bit in the current time
slot. The mechanism is referred to as the frame synchronization flywheel. The
flywheel counts the number of bits per frame and automatically rolls over the bit
count according to the programmed mode. The TSYNC or RSYNC input marks
the first bit in the frame. The mode specified in the RPORT_TYPE bit field and
TPORT_TYPE bit field in, and the start and end address of time slot pointer
determine the number of bits in the frame. A flywheel exists for both the transmit
and the receive functions for every port.
The flywheel is synchronized when the CX28560 detects TSYNC = 1 or RSYNC
= 1, for transmit or receive functions, respectively. Once synchronized, the
flywheel maintains synchronization without further assertion of the
synchronization signal.
The serial data stream that the CX28560 can manage consists of either packetized
data or unpacketized data. The CX28560 supports two types of data-stream
modes: HDLC and Transparent.
In transparent mode, message processing for every channel begins in the first
time slot marked as the first time slot in the channel’s frame structure. A user
must configure the first time slot in the RSIU Time Slot Configuration Descriptor
and TSIU Time Slot Configuration Descriptor.
For a channel configured in HDLC mode—either transmit or receive directions—
the channel waits for a synchronization signal from the internal frame
synchronization flywheel before starting processing a new message after channel
activation.
A frame synchronization signal must be provided once, after that, the CX28560
keeps track of subsequent frame bit location with its flywheel mechanism. The
frame alignment is not relevant when the port is configured in unchannelized
mode, although in unchannelized mode each time slot is treated as the first time
slot. By configuring more than one time slot in unchannelized mode, (i.e., using
TTS_ENDAD /RTS_ENDAD and TTS_STARTAD/RTS_STARTAD mechanism
to define one frame).
Mindspeed Technologies™
Advance Information
CX28560 Data Sheet
28560-DSH-001-B