cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 150

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Functional Description
6.1.2.3
6.1.2.4
6.1.2.5
6.1.2.6
6-4
Global Configuration
Global configuration is initiated by the host issuing service requests. Global
configuration specifies information used across the entire device including all ports,
all channels, and the EBUS.
For more information, refer to:
NOTE:
Interrupt Queue Configuration
Part of global configuration involves interrupt queue configuration. For more
information, refer to
POS-PHY Configuration
After global configuration has been completed, and the PCI bus set up, POS-PHY
Configuration should be performed by the host issuing service requests.
For more information, see the following registers in
Chip-Level Configuration
There a several registers that require configuration once per chip. They are configured
by the host issuing service requests. For further information, see
following registers:
•
•
• Receive POS PHY Control Register
• Transmit POS PHY Control Register
• Transmit Threshold Register
• Receive BUFFC Data FIFO Size Register
• Receive BUFFC Flexiframe Control Register
• Receive BUFFC Fragment Size Register
• Receive BUFFC Flexiframe Slot Time Register
• Receive SLP Maximum Message Length Register (x3)
• Transmit BUFFC Data FIFO Size Register
• Transmit BUFFC Flexiframe Control Register
• Transmit BUFFC Flexiframe Slot Time Register
Table 5-19, Global Configuration
Table 5-20, EBUS Configuration
Device identification at the PCI Configuration Level must be used to identify
the number of supported ports and channels in the CX28560, which in turn will
affect the CX28560’s configuration.
Mindspeed Technologies™
Chapter
Advance Information
5.0, Interrupt Queue Descriptor.
Register.
Register.
Chapter
5.0:
Chapter
CX28560 Data Sheet
28560-DSH-001-B
5.0, the