cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 41

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
Table 1-9. CX28560 POS-PHY Interface (Receive) (1 of 2)
28560-DSH-001-B
RFCLK
FRFCLK
RVAL
FRVAL
RENB
FRENB
RDAT[31:0]
FRDAT[7:0]
Pin Name
I/O
O
O
I
I
Table 1-9
interfaces—the data interface (32 bit, 100 MHz) and the FlowConductor interface
(8 bit, 100 MHz).
Ref Clk
FRFCLK
FRFCLK
FRFCLK
RFCLK
RFCLK
RFCLK
—
describes data transfer from the CX28560 to the system. This covers two
Mindspeed Technologies™
System to the CX28560 Receive FIFO Write Clock (RFCLK). RFCLK is used to
synchronize data transfer transactions between the system and the CX28560. Both
RFCLK and FRFCLK cycle at 100 MHz and signals are sampled on their rising edges.
Receive Data Valid (RVAL) signal. RVAL indicates the validity of the receive data
signals. RVAL will transition low when a receive FIFO is empty or at the end of a
packet. When RVAL is high, the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, and REOP
signals are valid. When RVAL is low, the RDAT[31:0], RPRTY, RMOD[1:0], RSOP,
and REOP signals are invalid and must be disregarded.
FRVAL indicates the validity of the receive data signals. FRVAL will transition low
when a receive FIFO is empty or at the end of a packet. When FRVAL is high, the
FRDAT[7:0], FRPRTY, FRSOP, and FREOP signals are valid. When FRVAL is low, the
FRDAT[7:0], FRPRTY, FRSOP, and FREOP signals are invalid and must be
disregarded.
Receive Read Enable (RENB) signal. The RENB signal controls the flow of data from
the receive FIFO’s. During data transfer, RVAL must be monitored as it will indicate if
the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, and REOP are valid. The system may
deassert RENB at anytime if it is unable to accept data from the CX28560. When
RENB is sampled low by the CX28560, a read is performed from the receive FIFO
and the RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, and RVAL signals are
updated on the following rising edge of RFCLK. When RENB is sampled high by the
CX28560, a read is not performed, and the RDAT[31:0], RPRTY, RMOD[1:0], RSOP,
REOP, and RVAL signals will not updated on the following rising edge of RFCLK.
The FRENB signal is used to control the flow of data from the receive FIFO’s. During
data transfer, FRVAL must be monitored as it will indicate if the FRDAT[7:0],
FRPRTY, FRSOP, and FREOP are valid. The system may deassert FRENB at anytime
if it is unable to accept data from the CX28560. When FRENB is sampled low by the
CX28560, a read is performed from the receive FIFO and the FRDAT[7:0], FRPRTY,
FRSOP, FREOP, and FRVAL signals are updated on the following rising edge of
FRFCLK. When FRENB is sampled low by the CX28560, a read is not performed and
the FRDAT[7:0], FRPRTY, FRSOP, FREOP, and FRVAL signals will not updated on the
following rising edge of FRFCLK.
Receive Packet Data Bus (RDAT[31:0] for data interface, FRDAT[7:0] for
FlowConductor Interface). The RDAT[31:0]/FRDAT[7:0] bus carries the packet
octets that are read from the receive FIFO and the in-band port address of the
selected receive FIFO. RDAT[31:0]/FRDAT[7:0] is considered valid only when RVAL/
FRVAL is asserted on the 32-bit interface; data must be received in big endian order.
In accordance with HDLC protocol, bit 0 of each byte is the first received bit at the
serial interface.
Advance Information
Description
Introduction
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